And now it's mid'24. Simple!It was supposed to be a early 2024 thing before "plans changed", no?
So we have reached the acceptance stage... quicker than I thought tbhThis is hilarious to watch.
Do none of you remember the slow creep up of IPC from Sandy Bridge to Skylake, and the complete stagnation after that for years? 15% increase is fine, good grief.
Psh I'm still bargaining. Give me 2-300MHz or else!So we have reached the acceptance stage... quicker than I thought tbh
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Who knew that the MLID slide from a year ago was dead on accurate. We just ignored it this entire time assuming it was too bad to be true.So we have reached the acceptance stage... quicker than I thought tbh
Personally I questioned it because the form I saw had "Moore's Law Is Dead" watermarked all over it.Who knew that the MLID slide from a year ago was dead on accurate. We just ignored it this entire time assuming it was too bad to be true.
bargaining stage : there is still room for T1 workloads to be higher IPC then nT , will have to wait a month to find out i guessWho knew that the MLID slide from a year ago was dead on accurate. We just ignored it this entire time assuming it was too bad to be true.
N5 -> N4 is an optical shrink, so everything (logic+sram+analog) gets shrunk.Fwiw, TSMC N4P comes with a 6% reduction in area for logic in comparison to TSMC N5,
Nope.so everything (logic+sram+analog) gets shrunk.
AVX-512 has many instructions, most of which are not useful for AI.I am hearing that avx-512 can assist AI a lot, but I know that it has other uses. It would seem this is the way to go today, and it AI goes away in the client space, it still has uses, where other AI hardware does not.
If so, I stand corrected.Nope.
It's just 6% moar logic density. Same analog and the exact same SRAM bitcell as usual.
Yeah, bleeding edge is eurgh.If so, I stand corrected.
Its not exactly earth shattering stuff. You could say the same about any platform with a big enough population.Edit: btw you guys should see Olrak's latest tweet...
Like his tweets are poise and smart. Don’t throw rocks in glass houses.If so, I stand corrected.
Edit: btw you guys should see Olrak's latest tweet...
What stage is this? /sIt feels to me like Zen5 as we see it today isn't the same Zen5 that was in the planning room three years ago. It seems like there were two plans: one plan for a successful roll-out of N3 and another that was a backup designed for N4. It looks like everything is getting the backup core. Not knowing how Zen5c behaves, I have no idea how it's going to shake out on N3.
I want to give Adroc and company the benefit of the doubt and believe that what they were shown/saw was the N3 plan. I know that that's probably wishful thinking. What was released sems to match well with that leaked slide, so it was probably done after the decision to fall back to N4 was made.
From what we are seeing, there's no way that Zen5 could have any more logic than it currently does and still keep the CCDs small enough to fit 16 on a package. So, it's certainly up against a wall as it is on N4.
Just my speculation.
No - I don't think so. There may be some things on the cutting room floor but not to that degree.It feels to me like Zen5 as we see it today isn't the same Zen5 that was in the planning room three years ago. It seems like there were two plans: one plan for a successful roll-out of N3 and another that was a backup designed for N4. It looks like everything is getting the backup core. Not knowing how Zen5c behaves, I have no idea how it's going to shake out on N3.
I want to give Adroc and company the benefit of the doubt and believe that what they were shown/saw was the N3 plan. I know that that's probably wishful thinking. What was released sems to match well with that leaked slide, so it was probably done after the decision to fall back to N4 was made.
From what we are seeing, there's no way that Zen5 could have any more logic than it currently does and still keep the CCDs small enough to fit 16 on a package. So, it's certainly up against a wall as it is on N4.
Just my speculation.
As is you'll have to look at patents if you're in a hurryCan we talk about the dual decoder/dual pipeline of Zen5?
I'm the one here who said there would have to be a Zen 5+ when TSMC 3nm becomes available in large quantities. The reason for it. Arrow Lake on 20A. Most people forget that Intel has a major node shrink coming. No more fake Intel generations. The efficiency gains by Intel will force AMD to move to 3nm before Zen 6. Wikipedia says that Zen 5 will be based on the fancy N4X. I doubt that. It was N4 and then N4P and now they say N4X. It's not 3nm but N4X is supposed to be the hotrod of 5nm silicon. I know they call it 4nm but it's still made on the 5nm process. They use 4nm to signify the advances in power, efficiency and density for more advanced cores than what standard 5nm can do.It feels to me like Zen5 as we see it today isn't the same Zen5 that was in the planning room three years ago. It seems like there were two plans: one plan for a successful roll-out of N3 and another that was a backup designed for N4. It looks like everything is getting the backup core. Not knowing how Zen5c behaves, I have no idea how it's going to shake out on N3.
I want to give Adroc and company the benefit of the doubt and believe that what they were shown/saw was the N3 plan. I know that that's probably wishful thinking. What was released sems to match well with that leaked slide, so it was probably done after the decision to fall back to N4 was made.
From what we are seeing, there's no way that Zen5 could have any more logic than it currently does and still keep the CCDs small enough to fit 16 on a package. So, it's certainly up against a wall as it is on N4.
Just my speculation.
No lmao.I'm the one here who said there would have to be a Zen 5+ when TSMC 3nm becomes available in large quantities
And it was 14%, bravo IDC.And to MLID, well you get to live another day, at least until LNC ends up being 15-20% IPC.