So early buyers of Zen5 will have to slot into their existing motherboard?https://www.hardwareluxx.de/index.p...ds-kommen-nach-dem-start-der-prozessoren.html
800 series motherboards won't be ready for Ryzen 9000 launch, they will arrive later. Actually OEMs were surprised that they are allowed to show them at Computex, that's why there's such a small number of models.
The 32% figure just doesn't appear out of thin air, and that's the issue.
Now that Mlid credibility has been improved, I'm inclined to believe the new core was plagued with bugs as mentioned recently.
Is it possible to design a CPU that doesn't perform that well in SPECint but manages to do well in pre-existing old binaries?Much changed hardware won't perform at it's full potential with old binaries but specint doesn't suffer from that. That's just a point - I don't know how Zen5 perform.
I agree that's what one should do: use the same version of compiler for all targets (gcc/LLVM), and use the same flags (usually -O2/-O3 and that's it).Anyone who tests with SPEC isn't using compiler optimizations for comparing performance across CPUs. They'll use the same GCC binary that every CPU gets.
AMD contributed its basic Zen5 support just in time to hit GCC 14.1 - aka the May 7th release. It remains to be seen the adoption among the SPEC submissions.Spec scores can be much higher than general application scores as specint can be compiled to cpu-specific optimizations. Much changed hardware won't perform at it's full potential with old binaries but specint doesn't suffer from that. That's just a point - I don't know how Zen5 perform.
So the design number count return back to Renoir days.Strix Point finally ends the plague of few AMD designs that started with Rembrandt. 100+ design wins for Strix Point is really good.
Let's just say them patches weren't quite real.AMD contributed its basic Zen5 support just in time to hit GCC 14.1 - aka the May 7th release.
RNR covered the entire stack, STX1 is strictly >$1200 SRP machines.So the design number count return back to Renoir days.
Can you share such a comparison for AVX2, NEON, AVX-512?But then one should also recompile to target ISA extensions available on a new CPU, and add that to the comparison.
Alas, even if I had such data available (I have some of them), I'd not be allowed to share them, sorry.Can you share such a comparison for AVX2, NEON, AVX-512?
By your employer or SPEC?I'd not be allowed to share them
My employer. SPEC doesn't prevent you from posting results, you just have to add a disclaimer saying the results are not official (I forgot the exact wording and it looks like spec.org is down at the moment; info should be here).By your employer or SPEC?
If you use SPEC rate 1T (which is what everyone uses in CPU design and in reviews), it's less than one hour IIRC. @SarahKerrigan might be able to say more about that.By the way, how long does running SPECint take on a modern CPU like Zen 4?
Is it possible to design a CPU that doesn't perform that well in SPECint but manages to do well in pre-existing old binaries?
I agree that's what one should do: use the same version of compiler for all targets (gcc/LLVM), and use the same flags (usually -O2/-O3 and that's it).
But then one should also recompile to target ISA extensions available on a new CPU, and add that to the comparison. Yes, that's extra work but worth the cost
That, of course, is something you can't do with SPEC since the source code is fixed.
Some parts of SPEC can be vectorized without changing sources with recent versions of non vendor compilers.You'd almost always have to change the source code to take advantage of ISA extensions. Just because a compiler supports AVX2 or SME or whatever doesn't mean it will actually get used. It will almost never get used with generic source code - you have to fiddle with the source code to figure out how the compiler expects it to be written to have a shot at it getting used - basically have to look at the assembler output until it does what you want.
That, of course, is something you can't do with SPEC since the source code is fixed.
My employer. SPEC doesn't prevent you from posting results, you just have to add a disclaimer saying the results are not official (I forgot the exact wording and it looks like spec.org is down at the moment; info should be here).
If you use SPEC rate 1T (which is what everyone uses in CPU design and in reviews), it's less than one hour IIRC. @SarahKerrigan might be able to say more about that.
Reportable runs take much longer, especially if you run the official non rate SPEC.
Is it possible to design a CPU that doesn't perform that well in SPECint but manages to do well in pre-existing old binaries?
I agree, but it has nonetheless some shortcomings inherent to its nature. For instance, code footprint is rather small compared to some software; on the other hand, huge workloads tend to be front-end bound beyond any hope (but they allow advanced studies SPEC doesn't such as instruction prefetch or the impact of larger structures in branch prediction). Also I'm not sure some JIT characteristics are well covered (though PERL and gcc share some characteristics).Not really. I guess you could design one that does well overall but flubs an individual subtest, and it happens IRL, but the specint suite does a pretty good job of covering common cases.
I agree, but it has nonetheless some shortcomings inherent to its nature. For instance, code footprint is rather small compared to some software; on the other hand, huge workloads tend to be front-end bound beyond any hope (but they allow advanced studies SPEC doesn't such as instruction prefetch or the impact of larger structures in branch prediction). Also I'm not sure some JIT characteristics are well covered (though PERL and gcc share some characteristics).
It gave us some funny results like AmpereOne with 16K i$ tho.Yeah, it's been said before, and I kind of agree with it, that SPEC's i-footprint is too small.
It gave us some funny results like AmpereOne with 16K i$ tho.
16K L1 with a really chungus 2M L2 strapped to a rather dinky core in general.Yeah, that was a deeply weird design decision
Well the thing exists mostly on paper. No CSP availability nor any merchant one.(Maybe their L2I latency is really good? I don't remember offhand if that's been disclosed.)