Compared to Apple at least, AMD's CAGR in IPC is around twice that of Apple's (I get5.56.23 CAGR IPC for Apple and 11.8 for AMD).
Edit: Starting in 2020 with Zen 3 and A14.
yep thats right. Thats both impressive and sad lol. Impressive that Apple still holds the IPC lead after the slowdowns and sad that AMD still cannot beat Apple despite executing better than Apple.
CPU architecture updates never aim to maximize IPC. Instead, they aim for a target area within a space with several optimization dimensions: IPC, single-core performance, SoC performance, performance per power, performance per area, feature set, security…Those numbers are chosen to make AMD look relatively better. Go back to 2017 and you'd see a different story.
It would be interesting to compare what Apple's growth rate was when their IPC was where Zen 4 is. I'm sure they were doing a lot better than they are now, because it is more difficult to increase IPC the higher it gets.
Will still be more efficient with the cache as there will be fewer requests to DRAM. At the halo end I think it makes sense to have the capability. Being the outright best means you can charge a premium for that. The end user interested in the extra efficiency can turn the clocks down if they wish.I don't even know if V Cache with higher clocks / Voltages is a good thing. It's biggest strength, the low power consumption, is literally because of that limitations. So maybe ZEN5 X3D will be another like 5% faster but lose it's power consumption advantage? Doesn't sound like a good tradeoff for me. Also Both CCDs with V Cache is unnecessary.
https://patents.google.com/patent/US11435798B2/en In this new patent from 2021, Apple introduced adaptive DPE which compares the estimated value with the physically measured value and adjusts the weight in accordance with the error. So the quality of the estimated number is quite good(especially for newer chips).I think these internal measurements be it powermetrics or the internal API geekerwan used are fine for measuring directional shifts *maybe* in CPU power, and just maybe, but overall they’re not that valuable.
For one, we don't actually know they use this simply because they have a patent for it. In 2021, Andrei Frumusanu measured M1 Max platform power vs external polling minus idle and received inconsistent results - he maintains powermetrics is itself still not fantastic.https://patents.google.com/patent/US11435798B2/en In this new patent from 2021, Apple introduced adaptive DPE which compares the estimated value with the physically measured value and adjusts the weight in accordance with the error. So the quality of the estimated number is quite good(especially for newer chips).
IPC gains are all fun for a discussion here in the forum, but to me it makes more sense to compare IPC+clock improvements/regression when comparing generations and there succes.This gen on gen is very convenient for AMD comparisons since it’s every 2 years unlike for Intel, Apple and ARM which is every year.
AMD’s IPC improvements YoY are mediocre.
Zen 3 -> Zen 4: around 22 months, ~6.5% YoY. ~13% total. Max clock increase as well
Zen 4 -> Zen 5: around 22 months, ~8% YoY. ~16% total. No max clock increase.
Apples done ~7% IPC improvement in around 7 months, M3 -> M4 and a clock increase. However, the last four years have been slower for Apple but let’s see if they improve.
I expected better from AMD, since they are proper chip company but it looks like after the OG Zen, only Zen 3 stands out.
Can we like wait for tests. I mean in tests without AVX-512 it won’t be that impressive. We already know CBR23 and CB 2024 scores for Strix Point. Nothing groundbreaking.
Those numbers are chosen to make AMD look relatively better. Go back to 2017 and you'd see a different story.
It would be interesting to compare what Apple's growth rate was when their IPC was where Zen 4 is. I'm sure they were doing a lot better than they are now, because it is more difficult to increase IPC the higher it gets.
CPU architecture updates never aim to maximize IPC. Instead, they aim for a target area within a space with several optimization dimensions: IPC, single-core performance, SoC performance, performance per power, performance per area, feature set, security…
For Apple for instance, increasing IPC gets more difficult not only because they are now on a high IPC level, but also because they are increasing clocks too. Making a high IPC core is easier if it doesn't have to clock high at the same time.
(For Apple, increasing IPC perhaps also gets more difficult because persons involved in the former large IPC advances are no longer working at Apple.)
Edit:
The CPU makers are not playing in exactly the same market segments. Thus, they don't have exactly the same optimization goals. This is one of the reasons why they end up advancing IPC at different rates. It's not simply "X increased IPC more than Y = X performs better than Y". Nor, "Z increased IPC by n in 2 years = they under-perform".
PPS,
and it's not IPC anyway, but iso-clock performance. ;-P
Also in 2020 after M1, there was a lot of people plotting graphs from the past and claiming how x86 was hopelessly behind and over.The goal wasn't to make AMD look good at all, but simply to compare. I chose 2020 for two reasons. First, because the discussion was about recent performance and 2020 lined up well with it being recent history and both having major core releases right around the same time that year.
That's interesting to show people that making predictions is error prone. The same applies to people claiming Intel or AMD are back in the game. They barely caught up with Apple.Also in 2020 after M1, there was a lot of people plotting graphs from the past and claiming how x86 was hopelessly behind and over.
Not a bad idea to basically confront those predictions with reality. I like the part where people looked down on "stupid GHz" (looking at Mr. Masters) and assuming Apple will not raise clocks in the future too. The path Apple's processors too fro then on is kind of amusing in that context.
100x speedup incoming:That's interesting to show people that making predictions is error prone. The same applies to people claiming Intel or AMD are back in the game. They barely caught up with Apple.
Now it will be interesting to see how things evolve for all the players.
I place my bet as I already did previously: we're getting dangerously close to the point where large IPC increases can't be done at reasonable area and power costs. So things will move more slowly in the coming years, or at least the major players will have similar IPC.
As all predictions, I will be proven wrong of course, and I hope I will as I want CPU to get faster
I'm talking about all purpose CPU not specialized units100x speedup incoming:
Did startup Flow Computing just make CPUs 100x faster? Here’s the white paper and FAQs
Read for yourself.www.theverge.com
It’s rare for me to disagree with every point of a post but I do. You can just adjust Ryzen Master or UEFI if you want higher efficiency. I’d love dual CCD VCache for certain productivity workloads. It would help compensate for the 16 cores being membw constrained by dual channel memory. A lot of folks like myself use the 5950 / 7950x as an affordable prosumer / workstation chip. For me the extra clocks would be worth it and dual CCD vcache would also remove thread scheduling concerns even if it doesn’t boost all workloads.I don't even know if V Cache with higher clocks / Voltages is a good thing. It's biggest strength, the low power consumption, is literally because of that limitations. So maybe ZEN5 X3D will be another like 5% faster but lose it's power consumption advantage? Doesn't sound like a good tradeoff for me. Also Both CCDs with V Cache is unnecessary.
It realistically shouldn't make a difference, but also it means the results don't necessarily correlate to 1T performance, as SMT is included when you do it this way. Plus also a 7700X is less likely to be memory bandwidth constrained than a 9950X as well.I was perplexed by that when I read the endnotes. Shouldn’t the result be the same if they compared 7950X v 9950X instead of 7700X v 9950X?
People don't seem to have got what I meant, so I'll elaborate with a warning: this is speculation. But if top bin Zen 5 CCDs are capable of hitting 5.7GHz at 1.2v, then it's theoretically possible for a potential 9950X3D to also clock both CCDs at a cap of 5.7GHz.+150MHz, to be exact. 7950X FMax is 5.85GHz.
There was a rumour that Zen 5 FMax is 6.1GHz. that could very well end up have been true given the clocks/voltage here, because that 5.7GHz at ~1.25v for relatively low end silicon implies that for the well binned stuff 5.7GHz at 1.2v may be possible. And in case you're wondering why 1.2v matters - that's V-Cache die territory.
100x speedup incoming:
Did startup Flow Computing just make CPUs 100x faster? Here’s the white paper and FAQs
Read for yourself.www.theverge.com
Because the cache is not shared between CCDs (or at least not without huge performance penalty)what was the issue of v-cache inability for both CCDs? voltage or thermals or both? I think they may have fixed it by now, just a matter of time
300mb L3 cache?? 😲😲😲 can store entire Stuff on the cpu itself, and with x2 bandwidth in new cache speeds...!!!!!
People don't seem to have got what I meant, so I'll elaborate with a warning: this is speculation. But if top bin Zen 5 CCDs are capable of hitting 5.7GHz at 1.2v, then it's theoretically possible for a potential 9950X3D to also clock both CCDs at a cap of 5.7GHz.
More importantly than us talking about a very fast X3D part: it nullifies the weird scheduling business needed for Zen 4 parts on X3D parts. If both CCDs can hit the same frequency, then the V-Cache CCD (aside from some extreme niche cases) will always be the faster CCD. Which means AMD just needs to rely on regular old CPPC to handle allocating workloads to cores, no need for the Game Bar nonsense we had last time.
Also means there's no need for a 9950X to have both CCDs to feature V-Cache.
But again, this is just a theory. Could very easily be wrong.
Because the cache is not shared between CCDs (or at least not without huge performance penalty)
Otherwise it would be interesting if the 3D parts had the same clock-speeds as the non 3D parts. That would mean that the 9800X3D would be 20% faster than the 7800X3D.
I couldn't remember the clock difference.Well, there is the 16% IPC + (potential) 10% clock speed advantage of 9800x3d vs. 7800x3d
I can only think it would still be a net win vs going to main memory.Because the cache is not shared between CCDs (or at least not without huge performance penalty)
It goes both ways. Its not like the x86 gang on twitter didn't make silly statements this year about Apple 's future too.Also in 2020 after M1, there was a lot of people plotting graphs from the past and claiming how x86 was hopelessly behind and over.
Not a bad idea to basically confront those predictions with reality. I like the part where people looked down on "stupid GHz" (looking at Mr. Masters) and assuming Apple will not raise clocks in the future too. The path Apple's processors too fro then on is kind of amusing in that context.
At a minimum, it is via cache coherency protocols.Because the cache is not shared between CCDs (or at least not without huge performance penalty)
It has been proven by measuring directly from the pin of the SoC that the error between the “real power” and the estimated one is less than 5%.For one, we don't actually know they use this simply because they have a patent for it. In 2021, Andrei Frumusanu measured M1 Max platform power vs external polling minus idle and received inconsistent results - he maintains powermetrics is itself still not fantastic.
TIL. Geekerwan found that?It has been proven by measuring directly from the pin of the SoC that the error between the “real power” and the estimated one is less than 5%.