Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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The Hardcard

Member
Oct 19, 2021
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Seems like the opposite of Bulldozer, if anything - BD was one frontend with two backends, Zen5 appears to be two frontends with one backend.
it appears to me to be a functional unit with resources split at the thread level. The implementation will obviously be different, but if the purpose of having two threads share some IP blocks while having separate paths through the unit, I see a possible connection.

From what I’ve seen it’s still early to say Bulldozer or the the opposite of, I’m just seeing the possibility of details that would amuse me.
 

SarahKerrigan

Senior member
Oct 12, 2014
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1,429
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it appears to me to be a functional unit with resources split at the thread level. The implementation will obviously be different, but if the purpose of having two threads share some IP blocks while having separate paths through the unit, I see a possible connection.

From what I’ve seen it’s still early to say Bulldozer or the the opposite of, I’m just seeing the possibility of details that would amuse me.

I've seen zero evidence that functional unit allocations are split between threads and that would sounds really undesirable if it were. Much of the entire advantage of SMT is ability to fill functional units in a dynamic manner using uops from all available threads.

So DozerBull. Gotcha!

Nah, Rezodllub.
 

The Hardcard

Member
Oct 19, 2021
124
177
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I've seen zero evidence that functional unit allocations are split between threads and that would sounds really undesirable if it were. Much of the entire advantage of SMT is ability to fill functional units in a dynamic manner using uops from all available threads.



Nah, Rezodllub.
How much evidence have you seen that they are not split?

I’m not here to make any claims, I just said I would find it amusing if they did it. If it turns out different, I don’t care.

It appears that there was some per thread thought that went to the design. Maybe I missed the hard facts that show where it ends.
 

SarahKerrigan

Senior member
Oct 12, 2014
593
1,429
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How much evidence have you seen that they are not split?

I’m not here to make any claims, I just said I would find it amusing if they did it. If it turns out different, I don’t care.

It appears that there was some per thread thought that went to the design. Maybe I missed the hard facts that show where it ends.

Because there's no reason to make them split. That would be microarchitecturally undesirable, since there's already the plumbing in there for the full set of functional units to be available to a single thread. "Prove they aren't split!" is like saying "prove the FPU doesn't switch to IBM hexadecimal FP encoding at random" - I can't prove it because I don't have a Zen5 in front of me, but it doesn't.
 

naukkis

Senior member
Jun 5, 2002
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634
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Because there's no reason to make them split. That would be microarchitecturally undesirable, since there's already the plumbing in there for the full set of functional units to be available to a single thread. "Prove they aren't split!" is like saying "prove the FPU doesn't switch to IBM hexadecimal FP encoding at random" - I can't prove it because I don't have a Zen5 in front of me, but it doesn't.

It could be clustered design. Like Alpha 21264. Both clusters could execute same thread but cluster-to-cluster register moves were needed that took one clock cycle. I see that it's possible to design front-end to handle that without real bottlenecks. Keep threads on own clusters when doing SMT. Split both clusters further to 2-threads possibility too if really wanted.
 
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tsamolotoff

Member
May 19, 2019
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It’s scores ~3700 as well in GB6.2 which doesn’t include SME.
Here's somewhat tuned 7950x3d results (my ccd1 is trash, can't clock above 5750 at all, surely dom can provide even better results on his binned CPUs):

Prefer cache:

Prefer frequency:
 

Mopetar

Diamond Member
Jan 31, 2011
8,004
6,445
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Someone leaked ahead of the Anandtech post that time?

That said. I think there is some point in WTFTech. They are actually quite good at scanning the tech leak landscape and summarizing findings. Even if they are not the best in accuracy, you have to give them credit for being quick. So if one applies a "common sense filter" to what is published, rendering what is reasonable vs BS, I think it's ok.

I'd much rather keep them as a player in the game than discarding them completely.

They properly attributed it, so readers can draw their own conclusions. They don't try to misrepresent themselves as portrayers of pure fact either. For people who like rumors, but can't be following every thread or every tech forum, they at least provide some utility.

Seems like the opposite of Bulldozer, if anything - BD was one frontend with two backends, Zen5 appears to be two frontends with one backend.

But it's a really big backend. AMD should partner with Sir Mix-a-Lot for their ad campaign.

So Bulldozer and Zen 5 have similar internal structure the same way apples and oranges share most of their DNA.

Didn't we already get yelled at recently for talking about Apple CPUs in this thread? Can we stay on topic. But while we're here, the recent performance claims, I think it might be more fair to say that Zen 5 shares a lot of DNA with bananas.
 

The Hardcard

Member
Oct 19, 2021
124
177
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Because there's no reason to make them split. That would be microarchitecturally undesirable, since there's already the plumbing in there for the full set of functional units to be available to a single thread. "Prove they aren't split!" is like saying "prove the FPU doesn't switch to IBM hexadecimal FP encoding at random" - I can't prove it because I don't have a Zen5 in front of me, but it doesn't.
The persistence at pressing your point against an expression of a concept is amusing. In fact that demonstrates why I’d be amused if it were done. All the “why did they do that, there’s no reason to” that would erupt from the crowd.

I don’t expect, suspect, speculate, support, hope for, anticipate, see signs of, or want a new Bulldozer. I just saw the reaction to what is now known and thought about how crazy the discussion would be if it was the case.

Actually, part of me does want one now, after seeing just the thought of it bring up some of the reaction I would find so funny.
 
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tsamolotoff

Member
May 19, 2019
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Here's somewhat tuned 7950x3d results (my ccd1 is trash, can't clock above 5750 at all, surely dom can provide even better results on his binned CPUs):

Prefer cache:

Prefer frequency:
This is a very random "benchmark", here's two more results, I've run them one to the next with no reboots or settings changed:

 
Reactions: lightmanek
Jul 27, 2020
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OR the frequency fluctuation on Zen 4 is pretty random?

Comparing both, the MT score variation in the subtests is much less than the ST one, so the all core frequency stabilizes better to a narrow range.
 

Hail The Brain Slug

Diamond Member
Oct 10, 2005
3,228
1,664
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I am getting just over 3100 ST on a stock 7950X with 6400C30 tuned ram.


I'll run on some flavor of Linux when I have a chance tomorrow, it's a more fair comparison of hardware to hardware if we want to make estimates for zen 5 and inevitably compare to Apple.
On Debian I am seeing 3262 single - https://browser.geekbench.com/v6/cpu/6668209

On Manjaro I am seeing 3290 single - https://browser.geekbench.com/v6/cpu/6668942
 

Cllaymenn

Junior Member
Jun 25, 2024
6
3
36
If we apply 16% uplift from 7950X to 9950X, that would put 9950X around 3800 ST in linux. Does that compare favorably against apple?
Geekbench 6 is so unreliable, its results seem to be random. You can't trust GB 6's results under any circumstances. I've already written about it on reddit. Just look at some of the highest results in the GB6 database.

one of many examples of nonsense. According to GB6, 14900 has the same MT performance as TR with 96 cores




 

Det0x

Golden Member
Sep 11, 2014
1,053
3,078
136
Here's somewhat tuned 7950x3d results (my ccd1 is trash, can't clock above 5750 at all, surely dom can provide even better results on his binned CPUs):

Prefer cache:

Prefer frequency:
7950X3D super maxed out


Older run with vanilla 7950X
 
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