C&C measured Zen 4's mop cache as 6.75k entries. Reducing it to 6k isn't a crazy reduction; seems like with a better decoder you don't have to rely on the mop cache as heavily. Also, if you can grab more mops from the mop cache, perhaps you don't need to keep so many stored in-flight?Quick question: The guy who tested Strix Point ES and noted structure reductions (notably uOP cache), do we know if this is true ? The slide for Zen 5 calls out 6K figure ,which matches Zen 4. I wonder how he got to the conclusion that Strix version had a reduction of that structure?
edit: It seems that Zen 4 has 6,912 Ops size, which is indeed a bit better than Zen 5's 6K
George Cozma: Now that brings me down to the micro-op cache. Again, in your diagrams you show 2 by 6 wide for the micro-op cache. Now in our conversations you have said that it’s a dual ported 6 wide op cache. What exactly does that mean for the throughput at any given time?
Mike Clark: So, it means that you know in in the best-case scenario we’re accessing the op cache with two fetch addresses and they both hit and we pull out the maximum we can pull out for any hit is 6 instructions and that if they both hit we can then deliver 12 instructions in one cycle out of the op cache.
Now we can’t always build 6 per entry. We don’t always hit or have them properly aligned so they can always hit in the op cache. So that’s why we actually, if you think about it, we’re 8 wide dispatch and be like, well, why would you grab 12 [ops] if you can only dispatch 8 [ops] but 12 [ops] is, you know the maximum and so it has to be a balance point that we pull more than we can, because sometimes we are inefficient and we can’t get all the instructions we want.
Desktop is a super-niche, no doubt. However, I'm not sure about the server market.I think it was done because the gains will be bigger in the enterprise / ai space and that is where the money is currently not desktop.
Desktop is a super-niche, no doubt. However, I'm not sure about the server market.
IMO the largest part are still hyperscalers providing their instances to run classic workloads like web servers, JVM apps, various implementations of microservices, Lambdas, etc. None of those need massive SIMDs.
What needs SIMDs is HPC/scientific workloads and engineering.
AI is better handled by even more specialized accelerators like Intel's AMX. So going for growing markets would be better off with a SKUs featuring some of these...
I have to agree. I think with a bigger xtor budget, they could've added in more "general purpose IPC". Regarding Zen 6, I think 10% is probably a safe assumption. I wouldn't assume 15% just because I don't foresee big architectural changes. If I were AMD, I would just focus on balancing the structures a little better, addressing corner cases where Zen 5 is weak, and then devote the bulk of the resources to ensure that the new packaging methodology works out of the gate. The IO die is entirely new too, so there's a lot of work that needs to happen there.All Zen5 is showing us so far is that AMD is putting greater comparative focus on the DC/Server side of Zen CCD performance over it's general purpose desktop capabilities. I'm not upset about it as it is still competitive on desktop, but, a full fat AVX-512 and apparently the other changes seem more relevant on server. Still, some of the quotes on here, especially the one about Zen5's front end being enlarged, but the rest of the core not being optimized for it yet, tell me that they were under some sort of not fully expected resource constraint. With the time available between Zen4 and Zen5, I don't think it was time. I still think it was N3B not being ready on time.
Going forward, I think that Zen6 may be more of a core performance jump than was originally anticipated. I don't expect miracles, but, more than the originally rumored 5% or so.
This is possible, although the original roadmap states just double-digits. This means 10 or more %.Going forward, I think that Zen6 may be more of a core performance jump than was originally anticipated. I don't expect miracles, but, more than the originally rumored 5% or so.
Sounds like the target is double digit (which is code for 10%).Going forward, I think that Zen6 may be more of a core performance jump than was originally anticipated. I don't expect miracles, but, more than the originally rumored 5% or so.
Double digits? Zen 6 WILL DOMINATE: confirmed to have 99% IPC uplift (cue RGT thumbnail)This is possible, although the original roadmap states just double-digits. This means 10 or more %.
Still, Zen 6 is a platform(SoC)-first refinement core. In a similar way the Zen 2 was.
No idea. Don't have those screenshots.can you comment if 43.9K = 230W PBO and the 45K (curve shaper) is also at 230W? Or is it at a higher PPT?
Based on looking at the source article at QuasarZone it looks to be like 42k is fully stock, 43.9k is PBO only (increasing power limit, no curve optimizer), 45.3K is adding curve shaper to that.No idea. Don't have those screenshots.
RTG: Ladies and Gentlemen, I was told from sources that Zen 6 will have mid-double digits IPC gain. Well, the middle between 10% and 99% is roughly 60%. Zen60% confirmed.Double digits? Zen 6 WILL DOMINATE: confirmed to have 99% IPC uplift (cue RGT thumbnail)
I frankly don't understand why people pretend that Zen 5 is somehow massively larger than Zen 4 area-wise. It's bigger, but it's not a SNC -> GLC type jump (area increase by 72%) that resulted in 19% IPC gain.
AMD's Zen line has been running 2 leapfrogging teams to produce a pair of cores - a new design and its refinement. Zen 1 + Zen 2; Zen 3 + Zen 4; Zen 5 + Zen 6. So producing an initial core implementing new ideas followed by its close refinement has been the way AMD's been operating since Zen 1.
However, in this case the new design is rather weak:
* Zen 1 scored 52% following low-IPC Family 15h.
* Zen 3 scored 19% with modest core area investment.
* Zen 5 scores 16% following the previous weakest generational IPC gain, blowing the core area quite a bit and being release 21 months after its predecessor at the same time.
It's sad AMD went all-in for AVX512 with Zen 5. Zen 4's approach could have stuck with us for more than a single generation.
I think your percentages are typo'ed, PBO+CO/CS was the highest score, should be the highest % uplift.Based on looking at the source article at QuasarZone it looks to be like 42k is fully stock, 43.9k is PBO only (increasing power limit, no curve optimizer), 45.3K is adding curve shaper to that.
The system pictured is on a 240mm NZXT AIO, presumably asetek, so not really a great cooler by any means.
These assumptions mean
Stock : 10.5% uplift
PBO Only: 15.5% uplift (7950X doesn't hit power limit so simply increasing PPT does nothing)
PBO + CO/CS: 15.2% uplift
No. PBO alone doesn't improve 7950X score without curve optimizer because it's not power limited, so only the 9950X gains here since it continues to scale up with power.I think your percentages are typo'ed, PBO+CO/CS was the highest score, should be the highest % uplift.
Also, fwiw, Zen 3 wasn't saddled by having to increase the FP width like Zen 2 was. Zen 3 was an optimization the in purist of senses. I don't recall Zen 3 introducing support for a niche feature or instruction that is known for requiring a lot of xtors.I frankly don't understand why people pretend that Zen 5 is somehow massively larger than Zen 4 area-wise. It's bigger, but it's not a SNC -> GLC type jump (area increase by 72%) that resulted in 19% IPC gain.
According to Friszchens Fritz, Zen 5 core on GNR is like 3.46 mm^2 against 2.73mm^2 without taking the L2 into account, a 27% increase. N4P is only 6% more dense compared to N5.
If anything, it's Zen 3 that is an alien. But that's mostly due to Zen1-2 being unoptimised designs with a lot of low-hanging fruit, which isn't surprising, given the company's financial struggles at the time of development.
Oh, I wasnt reading it correctly. I wonder if no-PBO 9950X is just pulling 190W PPT as rumored in WCCFTECH article a week or so ago and you need to enable PBO to get it to hit 230WPPT? Or is the 43.9K and 45.3K figures using more than 230W for the 9950X? Its very murky.No. PBO alone doesn't improve 7950X score without curve optimizer because it's not power limited, so only the 9950X gains here since it continues to scale up with power.
When we introduce CO for 7950X and CS for 9950X, the 7950X begins to make gains again.
Compare my scores for yourself.
7950X Stock: 38k vs. 42k
7950X PBO: 38k (unchanged from stock as mentioned above) vs. 43.9k
7950X PBO + CO: 39.3k vs 45.3k
Our ES angel has shown that with PBO and uncapped PPT, their ES will exceed 300W. I think it's just scaling well beyond 230W when PBO by itself is enabled, whereas the 7950X lingers around 210-230W even with PPT uncapped.Oh, I wasnt reading it correctly. I wonder if no-PBO 9950X is just pulling 190W PPT as rumored in WCCFTECH article a week or so ago and you need to enable PBO to get it to hit 230WPPT? Or is the 43.9K and 45.3K figures using more than 230W for the 9950X? Its very murky.
SMT = 1.3xWhen every thread has been used ,every thread use just 1*4 decoder(from 2*4 to 1*4),the IPC should decline?
It appears as if it's AMD's largest jump since OG Zen. It's definitely seems like it's AMD's largest architectural rework since then too. Take that as you will.I frankly don't understand why people pretend that Zen 5 is somehow massively larger than Zen 4 area-wise. It's bigger, but it's not a SNC -> GLC type jump (area increase by 72%) that resulted in 19% IPC gain.
According to Friszchens Fritz, Zen 5 core on GNR is like 3.46 mm^2 against 2.73mm^2 without taking the L2 into account, a 27% increase. N4P is only 6% more dense compared to N5.
If anything, it's Zen 3 that is an alien. But that's mostly due to Zen1-2 being unoptimised designs with a lot of low-hanging fruit, which isn't surprising, given the company's financial struggles at the time of development.
That SNC -> GLC jump again... Intel somehow has been pushing a stupidly large L2 cache since WLC. Besides, they hit 6GHz with a minor revision of that core. Zen 4 ate a large portion of that 7nm->5nm transistor budget to run at similar clocks.I frankly don't understand why people pretend that Zen 5 is somehow massively larger than Zen 4 area-wise. It's bigger, but it's not a SNC -> GLC type jump (area increase by 72%) that resulted in 19% IPC gain.
According to Friszchens Fritz, Zen 5 core on GNR is like 3.46 mm^2 against 2.73mm^2 without taking the L2 into account, a 27% increase. N4P is only 6% more dense compared to N5.
If anything, it's Zen 3 that is an alien. But that's mostly due to Zen1-2 being unoptimised designs with a lot of low-hanging fruit, which isn't surprising, given the company's financial struggles at the time of development.
Oh it does at -30co 2000fclk ~105w in heavy cpu limited gamesThis slide is so misleading again. 5800X3D doesn't use more than 80W in gaming, so there's a good chance 9700X took more energy in the test. TDP doesn't say anything for gaming workloads. Oh and 7800X3D uses 60W for being 20% faster than 5800X3D.