Some people on Xitter are saying it might be a packaging issue, whatever that means. Obviously, that's not in reference to the box the CPU comes in, although it would be funny if the issue was to fix a typo on the box.
That’s not what hardwareluxx is reporting. It’s also a hardware issue.According to AMD, it is not a design or packaging issue, but that they discovered that not all chips that were sent out went through QA, so they are sending out new chips to make sure they were properly tested before being sold/reviewed. See post #16,557.
Edit: If it was an actual issue with the chips, there's no chance they would be able to get them fixed and new ones out the door within a week or two. It would have to be either the QA testing miss as explained, or something wrong with the microcode/firmware that they could fix and push out quickly.
Maybe. Ryan seems to think it's a packaging issue as well:According to AMD, it is not a design or packaging issue, but that they discovered that not all chips that were sent out went through QA, so they are sending out new chips to make sure they were properly tested before being sold/reviewed. See post #16,557.
Edit: If it was an actual issue with the chips, there's no chance they would be able to get them fixed and new ones out the door within a week or two. It would have to be either the QA testing miss as explained, or something wrong with the microcode/firmware that they could fix and push out quickly.
More info, translated:That’s not what hardwareluxx is reporting. It’s also a hardware issue.
Not sure if this affect later Zen4, but the 3 7900x retail samples I got in Feb2023 that had ihs dated Jul-Aug 2022 all failed single thread corecycler AVX2 ycruncher/p95 at stock clock with no pbo or curve optimizer.Do you remember the launch problems of Zen 4 and burned burned sockets? Maybe AMD simply prefer a launch without bugs, as in September no one will remember if it was a late July or early August launch. They will however remember if their CPU is not working.
Conductor resistance is a big deal on advanced nodes and channel mobility increases with lower temperature, it's not just the conductors.
I mean, we have direct tests of power use vs. temperature and decades of practical overclocking experience to tell us that your theory is not correct. I honestly thought this was just established knowledge at this point, at least in overclocking communities.
Maybe. Ryan seems to think it's a packaging issue as well:
More info, translated:
Quality problems ensure a complete recall of the samples and also of the processors already delivered to the trade. All processors already delivered initially will therefore be replaced by a fresh production badge. AMD does not provide any information exactly which quality problems have occurred. But apparently it is a hardware problem that cannot be fixed by software.
They said that cold bug for the 9950X occur at -130°C, it means that at this temp the device is just too slow to work, wich say that at extremely low temps lowered transconductance has more impact than the lower resistances.
It s just that under LN2 they must make sure that the silicon reach a minimal temperature to be functional, because even with LN2 it will be way over this temp once it booted and is somewhat loaded.
I don't think the analog part is really a concern with modern CPUs, so it's most likely a hold time violation as the timing paths shift too far with the extreme temperatures and the data misses the edge window of the flip flop and fails to propagate to the next stage. It's not running too slow, the timings just weren't designed for that cold of operation.
Sure we can! This is the Internet!You can't get pissed about that.
But for time violation or interstage propagation to be too slow something has to limit the speed at wich the transistors are switching since lower resistance are supposed to help...
This means that the parasistic capacitances cant be charged fast enough, that is, that the provided current are too low, wich get us back to too low transistors conductance, actually low temp would be an advantage for higher speed if it werent for the transistors worse characteristics under this condition.
Yep, Im happy AMD is doing this. Cooled down a bit and a yeah better do it now and have a smooth launch.All I can add, is after the Intel fiasco, AMD wants to be SURE there is nothing at all wrong with what they send out, even if it causes a slight delay. 2 weeks is a slight delay. You can't get pissed about that.
Amen, brotha.Sure we can! This is the Internet!
If we can't have our daily drama... life becomes rather dull...Sure we can! This is the Internet!
Timing violation does not mean too slow, it just means off. It can also be too fast. Flip flops need a narrow window for the signal to be present and held in. If the signal is too early, it will also be a timing violation.
A hold time violation cannot be fixed by lowering the frequency (i.e., the signal is propagating too quickly), hence a cold bug will still be there even if you down clock as low as possible. Again, your theory is wrong.
I never use such sentences, i mean such arguments or rather lack of, you know, things like "it s well known that", "it s shown in real world tests" and so on.You can argue all you want, but real world tests have shown that it is not correct.
5.95 GHz, it's OC'd to hell. Someone having fun with an ES.Arrow Lake Leak got somebody excited enough to tune up a 9950X on Geekbench.
ASUS System Product Name - Geekbench
Benchmark results for an ASUS System Product Name with an AMD Eng Sample: 100-000001277-60_Y processor.browser.geekbench.com
View attachment 103765
It doesnt mater if it s too early as long as the clocks rising and falling edges are fast enough, once triggered the flip flop will keep its state for at least the duration of a clock cycle.
Same as above, if the signal is propagated swiftly this will allow for better level validation, what is a problem actually is when clocks signal hedges are not fast enough, at wich point levels coherency can no more be maintained since the flip flops cant be switched on/off correctly if the clocks signals are not well formed, no matter what are the data signals levels and shapes.
I never use such sentences, i mean such arguments or rather lack of, you know, things like "it s well known that", "it s shown in real world tests" and so on.
Make me a deal.So who wants to be guinea pig and buy a CPU from the first batch now, unless AMD discloses what the actual problem was and how well it could be fixed?
You may not like that real world tests prove your theory wrong, but that is the ultimate evidence. You can theorize all you want, but if the real life tests show something very different or even the opposite, then your theory is clearly wrong. The proof is in the pudding.
Hold time violations are also called minimum delay violations because the signal is propagating too fast,
The pudding interior say that time violation occur mainly when the data signal is too late.
It can occur if the signal comes too early but in this case it s only if the clock is too high and as a consequence that there s not enough time for the stage to be triggered during the relevant clock cycle as to hold the desired value.
So assuming that frequency is low enough at the start there will be no time violation by other mean than the transistors not switching fast enough, that is, too low transconductance to charge parasistic capacitances in due time, i.e, signal being too late as a result.
Hold violation happen when data is too fast compared to the clock speed. For fixing the hold violation, delay should be increased in the data path.
*Note:* Hold violations is critical and on priority basis in comparison are not fixed before the chip is made, more there is nothing that can be done post fabrication to fix hold problems unlike setup violation where the clock speed can be reduced. The designer needs to simply add more delay to the data path.