Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[adroc_thurston]

Not in the sense of being a completely uncompetitive product. It looks like AMD made some odd choices, tried some new tricks, and performance is kind of underwhelming, but it's not meaningfully worse than Zen4 on any axis and is better on some others.

Yeah, this is like Cortex-X3, massive changes for meh bumps.
Kinda ass.

Perhaps they really wanted to ensure perf/watt at the very start of the curve is competitive, so they increased the -C core count. I agree though, I'm confused about the P+E core arrangement too, and I'm really surprised out of the couple interviews with AMD employees we had, no one really asked them about this...

It's cost.

 

[QuickyDuck]

Wow, efficiency is better than my expectation, basically on part with X elite.

Couldn't decide which one is bigger disappointment though.

 

[GTracing]

Not in the sense of being a completely uncompetitive product. It looks like AMD made some odd choices, tried some new tricks, and performance is kind of underwhelming, but it's not meaningfully worse than Zen4 on any axis and is better on some others.

Folks making the Dozer comparison need to remember that Intel was doing 50%+ more iso-clock ST int against it.

I would add that Bulldozer used more power than it's predecessor and nearly twice as much as Sandy Bridge. Zen5 has quite decent power consumption.

 

[LightningZ71]

The arrangement makes more sense when you remember the other rumors for Strix Point. It was supposed to have a decent chunk of MALL cache that got axed for the larger NPU. That MALL cache makes Strix Point look a lot mire like Alder Lake/Raptor Lake to an OS scheduler, with a combo of faster cores with large L2 and a slight latency hit last level cache (L3 there) and a group of more numerous, slower cores that have more limited cache (shared L2) with similar access to a hugher latency LLC.

In the universe with the MALL cache, the split CCX, limited cache arrangement makes more sense. If they had gone with a single CCX with 4 X zen5-512b cores and 4 x Zen5c-512b cores with 32MB L3, and completely ditched the last 4 Zen5C cores, they would be in about the same footprint on the chip and likely have fewer performance oddities while having situations with much higher performance due to the big 32MB L3.

 

[SarahKerrigan]

I would add that Bulldozer used more power than it's predecessor and nearly twice as much as Sandy Bridge. Zen5 has quite decent power consumption.

Yeah. BD was a massive misfire. It was not "oh, well, it's only a few percent faster than its already-very-competitive predecessor in slightly-moderately lower power." It was "runs very hot, loses by a massive margin to Intel on ST and barely hangs on with MT despite double the core count."

It was dire.

 

[poke01]

No. Zen 5 isn’t bulldozer but it’s also not the mythical core that Apple etc will take years to catch up to. That assertion still annoys me.

 

[poke01]

Wow, efficiency is better than my expectation, basically on part with X elite.

Couldn't decide which one is bigger disappointment though.

Strix Point still beaten by last gen M3 with a smaller battery. There is a reason why AMD made no battery comparisons.

 

[jdubs03]

No. Zen 5 isn’t bulldozer but it’s also not the mythical core that Apple etc will take years to catch up to. That assertion still annoys me.

I think the M4 is that mythical core for now. I suspect the M4 Pro/Max will be quite impressive.

Btw I found this… 1207 pts in CB24 multi-core (performance mode).

Asus ProArt P16 review (2024 H7606WI model, AMD Ryzen AI 9 HX 370, RTX 4070)

This is my detailed review of the 2024 Asus ProArt P16 H7606 lineup of workstation portable laptops.

www.ultrabookreview.com

 

[biostud]

Since there has been made som z790 boards with camm2 slots does AM5 chips in theory supports camm2 modules or will it require a new CCD/memory controller and socket?

 

[CouncilorIrissa]

Physical design team has carried this design hard, it seems. Its PPA would be seen as not good if it wasn't for the impressive L3 shrink.

 

[gaav87]

Is the chinese leak for the recall TYPO legit ? Im 13% faster in avg and 54% in minimum fps then that 9700x on 5800x3d in cyberpunk ? If its true then im kinda pissed.

 

[poke01]

Btw I found this… 1207 pts in CB24 multi-core.

The 54watt version?

 

[Philste]

Btw I found this… 1207 pts in CB24 multi-core (performance mode).

1200 is the theoretical max if we take 1000 result from Computerbase at 3.43GHz Allcore. With 5.1 on All 4 normal Cores and 3.7 on All c-cores we land basically exactly at 1200.

 

[Philste]

The 54watt version?

Full gas, see above, with posted clocks by computerbase we can see that everything above 1200 (of course with slight margin of error) is impossible.

 

[StefanR5R]

So it is indeed Zen5%.

Regressing in the GCC subtest after all the accolades about that zero-bubble, 2-branches BPU with 16k L1 BTB... Jesus, this is Bulldozer vibes.

Reminder: For comparison of core generations, variable clock runs on different laptops are not as informative as

• fixed clock runs,¹ or
• variable clock runs but with task energy measured, or
• not as good but better than nothing: variable clock runs but with clock speed histogram.

No use to get all emotional before measurements of this kind become available.²

________
¹) Or even better, fixed clock runs with task energy.
²) Clock speed histograms for Cinebench 2024 are reported by Computerbase, for a start.

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

I think I read that Mike Clark said they worked on four different Zen 5 designs?

z5c-256, z5c-512, z5-256, z5-512

In addition, z5c-256 (edit: Strix Point) and z5c-512 (Turin-dense) are on different process nodes.
And Andreas Schilling claims that Strix Point (z5-256+z5c-256) and Granite Ridge (z5c-256) are on different processes too (N4P vs. N4X).

I am idly wondering if FPU datapath widths is really the only microarchitectural difference between the designs. (I.e., aside from differences at uncore — such as L3$ size per CCX and IF width per CCX — and at the physical design.)

 

[SarahKerrigan]

Stages of an AMD Microarchitecture's Hype

1. Wild exuberance and extreme optimism toward rumors
2. Dismissing of less positive rumors
3. Core is announced; looks mid
4. AMD must be sandbagging the numbers; the real ones will be higher
5. ES numbers leak
6. Perf is mid, it must just be because it's an ES
7. Core launches and is reviewed; proves to be mid
8. Compiler/application optimization will improve it! Anyway, the next one will be amazing!
9. Go to step 1

 

[adroc_thurston]

Stages of an AMD Microarchitecture's Hype

1. Wild exuberance and extreme optimism toward rumors
2. Dismissing of less positive rumors
3. Core is announced; looks mid
4. AMD must be sandbagging the numbers; the real ones will be higher
5. ES numbers leak
6. Perf is mid, it must just be because it's an ES
7. Core launches and is reviewed; proves to be mid
8. Compiler/application optimization will improve it! Anyway, the next one will be amazing!
9. Go to step 1

now that's cope, roll the clock back and see what people expected from Z3/Z4.

 

[Jan Olšan]

Is there any review measuring power draw during strictly single-thread tasks? (To see the ST boost power of a single core.)

Edit: https://www.computerbase.de/2024-07.../#abschnitt_der_amd_ryzen_ai_9_hx_370_im_test
Apparently is runs single core Cinebench R24 at 18-20W SoC Power, which isn't worst. At least in the Zenbook S16 device tested.

It doesn't quite sustain its maximum ST boost 100% of time, it starts at 5.1 GHz but then drops to 5.0 GHz over time. (People keeping boost on and "calculating" IPC by dividing performance by assumed clock like AnandTech used to do in the past may get wrong result).

I am idly wondering if FPU datapath widths is really the only microarchitectural difference between the designs.

You probably meant unit widths by "datapath", but incidentally, load/store are kept 512bit on the 256bit variants.

 

[SarahKerrigan]

now that's cope, roll the clock back and see what people expected from Z3/Z4.

32%

Have you seen Strix???

Just wait till Zen5 launches!! You'll all see!

 

[adroc_thurston]

32%

Have you seen Strix???

Just wait till Zen5 launches!! You'll all see!

Yes, a rather unique slip.
Now let's see Paul Allen's Zen4.

 

[Josh128]

Is the chinese leak for the recall TYPO legit ? Im 13% faster in avg and 54% in minimum fps then that 9700x on 5800x3d in cyberpunk ? If its true then im kinda pissed. View attachment 104072

Must state the obvious obligatory different GPUs, but further than that-- does anyone remember some techtuber/leaker saying they saw something really weird in CP2077 with either Zen 5 or 9700X (dont remember which)? Somebody help me, I cant recall who it was but I distinctly remember it. This could be what they were alluding to.

 

[SarahKerrigan]

Yes, a rather unique slip.
Now let's see Paul Allen's Zen4.

All I suggest is that perhaps next time you should be less confident and aggressive about things that turn out to be hilariously wrong.

I actually think Zen5 looks decent, as an intergenerational bump, but it bears no resemblance to what you were hyping.

 

[adroc_thurston]

All I suggest is that perhaps next time you should be less confident and aggressive about things that turn out to be hilariously wrong.

They've been doing beat and raise in CPUs since the OG Zen.
Even Z4, the nothingburger tick was that. Come on.

I actually think Zen5 looks decent, as an intergenerational bump, but it bears no resemblance to what you were hyping.

PPA-wise it does not crimes but 1t CAGR is severely lacking.

 

[Josh128]

Yeah, this is like Cortex-X3, massive changes for meh bumps.
Kinda ass.

It's cost.

The weird thing is, apparently they have a 16 core CCX design completed presumably for use with some form of Zen 5. Makes you wonder why they went 4+8 when they could have apparently done 8+8 on same CCX for Strix. 4 extra cores doesnt seem like it would have busted the area budget?

 

[CouncilorIrissa]

Yes, a rather unique slip.
Now let's see Paul Allen's Zen4.

The Unique Slip 2: Electric Boogaloo (granted that was a GPU).

I'll show myself out.