Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[mostwanted002]

M1->M4 is +38% clock alone, plus incremental iso-clock improvements. What's peak x86 ST done in the same time?

Since when do higher Clock numbers directly translate to improvement in newer architecture?
And unironically, that's proving the point. Throwing more clock speed at the problem with no significant gains and it was proved by Apple themselves when they didn't even bother to compare M4 to M3 in their presentation, and later on when independent researchers/enthusiasts proved that except for the gains from NPU in certain tasks, it's close to no gains in all other areas.

Is this more "x86 is secretly way ahead at REAL applications" stuff?

There's no secret to that.

 

[SarahKerrigan]

Since when do higher Clock numbers directly translate to improvement in newer architecture?
And unironically, that's proving the point. Throwing more clock speed at the problem with no significant gains and it was proved by Apple themselves when they didn't even bother to compare M4 to M3 in their presentation, and later on when independent researchers/enthusiasts proved that except for the gains from NPU in certain tasks, it's close to no gains in all other areas.

Being able to consistently scale clocks across gens is not trivial.

There's no secret to that.

Cool, can you link the industry-standard benchmarks?

 

[Hitman928]

M1->M4 is +38% clock alone, plus incremental iso-clock improvements. What's peak x86 ST done in the same time?

Zen 2 -> Zen 5 is ~85% ST improvement IPC + clocks.

 

[SarahKerrigan]

Zen 2 -> Zen 5 is ~85% ST improvement IPC + clocks.

Nifty. Not bad at all. That GB6?

 

[Hitman928]

Nifty. Not bad at all. That GB6?

Should be SPEC. I took the IPC increases for each generation (SPECint verified) times the increase in clock speed. The one kind-of caveat is that I used the real boost clock for Zen 2, not the advertised one, because Zen 2 many times couldn't actually hit its boost clock, let alone sustain it, so I used the measured boost clock from the Anandtech review. For Zen 4/5 I used the advertised boost clock, even though they can actually typically hit slightly higher if cooled well enough.

Edit: For M1 -> M4 I get ~55% increase with clocks + IPC.

 

[DaaQ]

Why did SarahKerrigan go grey with a line through it? or anyone for that matter, what causes that?

 

[esquared]

Why did SarahKerrigan go grey with a line through it? or anyone for that matter, what causes that?

They disabled their account.

 

[DaaQ]

They disabled their account.

Thank you, always wondered what it meant.

 

[maddie]

Sudden, some nasty PMs?

 

[Hitman928]

Thank you, always wondered what it meant.

Very unfortunate. There aren’t many here with actual technical backgrounds who post with any kind of frequency.

 

[poke01]

IMO, the whole reason why Lunar exists is because of M1. It will continue to exist thru panther lake and so on on the U series.

AMD and Intel consider Apple to be a competitor in mobile because they end up in the top 5 of IDC charts. While some here don’t use Apple that doesn’t mean some can’t discuss it here. Especially since AMD wanted reviewers to use M3 in the CPU benchmarks. All of us here know that not all windows applications can run on M chips but some are taking it too personal. x86 won’t die it will continue to get better if there is pressure from other ISA’s but seems like people are not pleased when AMD isn’t at top of the charts.

 

[DaaQ]

IMO, the whole reason why Lunar exists is because of M1. It will continue to exist thru panther lake and so on on the U series.

AMD and Intel consider Apple to be a competitor in mobile because they end up in the top 5 of IDC charts. While some here don’t use Apple that doesn’t mean some can’t discuss it here. Especially since AMD wanted reviewers to use M3 in the CPU benchmarks. All of us here know that not all windows applications can run on M chips but some are taking it too personal. x86 won’t die it will continue to get better if there is pressure from other ISA’s but seems like people are not pleased when AMD isn’t at top of the charts.

Well it should go into a generic IPC Apple v x86 thread imo, or just a plain IPC thread.

They are mobile due to laptops, phones are not in the equation I think.

Granted Jim Keller did go there, and we are apparently seeing the fruits of the labor, but still. He has been everywhere.

IMO x86 needs to drop some backwards compatibility, even IF I cannot run Diablo 1.

Still needs it's own thread.

 

[Jan Olšan]

M1->M4 is +38% clock alone, plus incremental iso-clock improvements. What's peak x86 ST done in the same time?

Well, if we start in 2020 (M1) and take 5950X compared do 7950X (2022), it's not so shabby https://browser.geekbench.com/v6/cpu/compare/4649694?baseline=111839

We'll see how well does 9950X (2024) turn out after reviews https://browser.geekbench.com/v6/cpu/compare/7035563?baseline=111839
Could be +55% to +60% in total. 16% out of that is clock gain I think?

 

[Shmee]

I will miss her very much, just like Jim Raynor did when the Zerg got her.

 

[Joe NYC]

Doesn't Strix Point? How was the MALL to work without that?

I think it could better be described as shared, rather than unified.

Meaning CPU can allocate from the pool, GPU allocates from the same pool, but once GPU owns its chunk of memory, CPU can't use it and vice versa.

I think it would likely take a rewrite for DirectX to be able to use memory in unified manner. Which means that APUs are Unified memory capable, but Windows is not.

 

[Jan Olšan]

That's true. People keep obsessing over IPC when it is only one component (albeit a very nice component) of performance.

Recalling how the twitter debates looked in year 2020 with the types of Maynard Handley (lol) or Jon Masters (a bit more regrettable) posting those "increasing GHz is STUPID" / "Intel only knows how to GHZ" comments left and right.... fast forward to today, 2024 - it is at least a bit amusing.

 

[Joe NYC]

It doesn't.

No, 4C is becoming the standard from either vendor.

Is it possible for Kraken to have 4 full and 4c cores on one ring, with one 16 MB L3 cache?

That would save die area, complexity and reduce some performance degradation corner cases.

It seems to me this would be a worthwhile investment of resources to get this kind of design out, assuming Kraken will be AMD's volume part, and also competing with Lunar Lake.

 

[SteinFG]

die shot annotation


Shows only 16 lanes present, sad but confirmed what I was thinking:

So after the recent tech brief, it's known that all Zen 5 APUs wil have 16 PCIe lanes. That's 4 less than in Phoenix.

8500G's curse of only 4 GPU lanes will come to 9700G and 9600G.

 

[adroc_thurston]

assuming Kraken will be AMD's volume part

Yea.

and also competing with Lunar Lake.

Lmao no very different segments.

Is it possible for Kraken to have 4 full and 4c cores on one ring, with one 16 MB L3 cache?

Yeah but that ain't free either.

 

[SteinFG]

Lmao no very different segments.

What's the difference except the size that SOC + RAM take up on a PCB? PL1 (17W) and PL2 (30W) seem similar to some current strix laptops, Kraken is probably in the same vein.

 

[Joe NYC]

Lmao no very different segments.

It's hard to make any sense out of Intel's product segmentation, considering Intel's product line, starting 2025 being:
- Meteor Lake
- Lunar Lake
- Raptor Lake

As far as Kraken, it seems like there would be some overlap with Lunar Lake and some overlap with Raptor Lake.

Meteor Lake in 2025 will be a head scratcher (being obsolete), unless there is some meaningful refresh.

Yeah but that ain't free either.

Starting from Strix Point, and dropping 4 Dense cores, and not dropping the separate L3 for Dense cores would be very dumb.

Hopefully, since AMD is taking extra 6 months to release Kraken, AMD is using this time to get this level of optimization. It is investment of resources, but if AMD has an ambition of moving the needle on market share significantly, and succeeds by shipping Kraken in high volume, those investment would be repaid.

Not to mention the fact that Kraken would be more performance competitive with only a single ring bus and only a single L3 cache.

 

[naukkis]

Starting from Strix Point, and dropping 4 Dense cores, and not dropping the separate L3 for Dense cores would be very dumb.

Hopefully, since AMD is taking extra 6 months to release Kraken, AMD is using this time to get this level of optimization. It is investment of resources, but if AMD has an ambition of moving the needle on market share significantly, and succeeds by shipping Kraken in high volume, those investment would be repaid.

Not to mention the fact that Kraken would be more performance competitive with only a single ring bus and only a single L3 cache.

Biggest problem for mobile isn't performance but battery life. Having separate low-power cluster will extend battery life as it can optimized better for low power and high performing parts can clock gated when not needed. But AMD's strix point version of that idea is not ideal - why have 8 cores on low power cluster making it to use more power and same time lower high perfromance mode?

 

[Joe NYC]

Biggest problem for mobile isn't performance but battery life. Having separate low-power cluster will extend battery life as it can optimized better for low power and high performing parts can clock gated when not needed. But AMD's strix point version of that idea is not ideal - why have 8 cores on low power cluster making it to use more power and same time lower high perfromance mode?

Interesting question. Some metrics of how much the low power cluster uses vs. high performance cluster would be helpful.

But it seems to me that there is ability to shut down cores individually, and if all of the performance cores are asleep, only low power cores are active, I don't see where the difference of "cluster" would come in.

Maybe the cluster could go between high power and high efficiency just depending on which cores are awake and running code. And it would preserve the data in L3.

Having to perform a number of unnecessary memory accesses to re-populate L3 on the "correct" cluster could eliminate all power savings.

 

[Nothingness]

Sudden, some nasty PMs?

You don't need nasty PM to get frustrated by the way some people behave on this forum. Brand loyalty seems to have very adverse effects and sometimes makes reasonable technical discussion very difficult. That's also why Andrei left the forum some years ago.

That won't change a thing here for most, they'll stay in their bubble. But the loss of Sarah is significant.

Sorry for being off topic, but I humbly think it was worth saying.

Now let's get back onboard the hype train.

 

[Abwx]

You don't need nasty PM to get frustrated by the way some people behave on this forum. Brand loyalty seems to have very adverse effects and sometimes makes reasonable technical discussion very difficult. That's also why Andrei left the forum some years ago.

That won't change a thing here for most, they'll stay in their bubble. But the loss of Sarah is significant.

Sorry for being off topic, but I humbly think it was worth saying.

Not that i want to extend the OT but hope that she ll get here again at some point, her posts are often very insightfull.