Jesus. Losing another very knowledgeable poster to brand loyalty warfare, smh.You don't need nasty PM to get frustrated by the way some people behave on this forum. Brand loyalty seems to have very adverse effects and sometimes makes reasonable technical discussion very difficult. That's also why Andrei left the forum some years ago.
That won't change a thing here for most, they'll stay in their bubble. But the loss of Sarah is significant.
Sorry for being off topic, but I humbly think it was worth saying.
Now let's get back onboard the hype train.
Jesus. Losing another very knowledgeable poster to brand loyalty warfare, smh.
Not surprising, some of yesterday' claims to refute her posts were downright outrageous.
On the off chance that you're reading this, we'll be missing you Sarah.
Interesting question. Some metrics of how much the low power cluster uses vs. high performance cluster would be helpful.
But it seems to me that there is ability to shut down cores individually, and if all of the performance cores are asleep, only low power cores are active, I don't see where the difference of "cluster" would come in.
Maybe the cluster could go between high power and high efficiency just depending on which cores are awake and running code. And it would preserve the data in L3.
Having to perform a number of unnecessary memory accesses to re-populate L3 on the "correct" cluster could eliminate all power savings.
Jesus. Losing another very knowledgeable poster to brand loyalty warfare, smh.
Not surprising, some of yesterday' claims to refute her posts were downright outrageous.
On the off chance that you're reading this, we'll be missing you Sarah.
When core on ringbus is active whole ringbus has to powered. High-speed optimized ringbus will eat lots of power. So Intel did introduce low power cluster without ringbus. AMD instead put whole 8 stop ringbus on their low-power cluster - which is pretty braindead way to do low power cluster - not very low power but same time also not high performance.
Just for the record, I had NOTHING to do with it. I had quieted down after her Parallels GB link and I have a terrible cold and associated headache anyway. I'm pretty sure something happened. Either she got a nasty PM from someone or she got tired and weary on realizing how much time she wasted arguing here and decided her time deserved being spent doing something more productive. Hopefully she will be reading the forums, as an observer only.This is why most sites that don't ban trolls who are just arguing stupid stuff all the time end up degenerating over time. The smart people leave because it isn't worth it, then the troll to smart people ration is worse and more smart people leave. You see this everywhere, except maybe a few niche sites that few know about - and you have to treat it like fight club or once the trolls discover it its all over.
Which is why an 8+4 setup would have been perfect. 8 Zen5 cluster is used for maximum performance (both ST and MT), while the 4 Zen5C cluster would be used as a low power island for power efficiency. This is what ARM SoC vendors do. Use the small cores for power efficiency, and use the large cores for performance scaling.When core on ringbus is active whole ringbus has to powered. High-speed optimized ringbus will eat lots of power. So Intel did introduce low power cluster without ringbus. AMD instead put whole 8 stop ringbus on their low-power cluster - which is pretty braindead way to do low power cluster - not very low power but same time also not high performance.
So that's kind of what I thought. So, in a way, having an 8 stop ringbus with mixed type cores may not use much more power than a "low power" 8 stop ringbus with strictly power efficient cores.
We will see how AMD eventually implements this. It would take design resources to implement a single ring bus with mixed types of cores. Unknown how simple or difficult that would be.
But I think there would be a nice upside in die area efficiency, possibly even power efficiency, and definitely in performance.
@Jan Olšan great article(I think you are the author right?). Goes in depth and nicely explained.Nice article about Zen5 architecture
Zen 5: AMD's biggest innovation since first Zen [expanded deep dive] - HWCooling.net
Introduction: Desktop Zen 5 fits in the same die area as Zen 4It’s roughly two weeks until AMD releases processors with the new Zen 5 architecture. This week, we finally got proper details on these CPUs’ architecture, which AMD revealed at the Tech Day event. So, we can now break down the...www.hwcooling.net
Itanium crying a deep cry from the bottom of the sea...That worked a total of zero times in the history of computing.
Clearly needs a bios update to enable the last 300Mhz. AMD was sandbagging after all!!
It seems David has issues getting STX to boost to 5.1
thats on linux too. So Geekbench was reporting the right clocks then. So its okay for AMD/Asus to advertise fake boost clocks and all Strix machines have fans but when Apple doesn't maintain ST clocks on a fanless machine its a scam...
It seems David has issues getting STX to boost to 5.1
Let's see if other thin&light devices behave the same way.thats on linux too. So Geekbench was reporting the right clocks then. So its okay for AMD to advertise fake boost clocks and all Strix machines have fans but when Apple doesn't reach maintain ST clocks on a fanless machine its a scam...
+1Jesus. Losing another very knowledgeable poster to brand loyalty warfare, smh.
Not surprising, some of yesterday' claims to refute her posts were downright outrageous.
On the off chance that you're reading this, we'll be missing you Sarah.
Looking into it yes it seems the smaller Asus laptops cannot reach the 5.1GHz. The 16" Zenbook seems fine tho.Let's see if other thin&light devices behave the same way.
Thicker devices seem to handle the boost clock fine.
What has the bad cooling implementation of one OEM to do with the chip capabilities? In the notebookcheck.net review herethats on linux too. So Geekbench was reporting the right clocks then. So its okay for AMD/Asus to advertise fake boost clocks and all Strix machines have fans but when Apple doesn't maintain ST clocks on a fanless machine its a scam...
No wonder AMD didn't increase boost clocks this gen. They couldn't!
ProArt is high performance laptop. It has cooling that can handle high tdp. Average laptop can't.What has the bad cooling implementation of one OEM to do with the chip capabilities? In the notebookcheck.net review here
AMD Zen 5 Strix Point CPU analysis - Ryzen AI 9 HX 370 versus Intel Core Ultra, Apple M3 and Qualcomm Snapdragon X Elite
Notebookcheck takes a look at the new AMD Zen 5 Ryzen AI 9 HX 370 processor and compares it with the Intel Core Ultra, Apple M3 Pro and Qualcomm Snapdragon X Elite.www.notebookcheck.net
there are the ProArt series' results with noticeably higher performance even in ST. So it's not the chip.
Zenbook was tuned too much down on power limits and cooling capabilities to keep it (ridicously) thin.
80W is not "high TDP", most of the laptops out there are more than capable to hadle these and there are out there 15,6" chassis with 150+W weighting slightly more than 2kg and Strix halo which is designed for light laptops as well can go up to 125W. ZenbookS16 is so thin that one of the review I read complained they had issue with one of the USB-C ports barely fitting in the chassis.ProArt is high performance laptop. It has cooling that can handle high tdp. Average laptop can't.
Umm, the ZenbookS and ProArt are 2 different laptops?80W is not "high TDP", there are out there 15,6" chassis with 150+W weighting slightly more than 2kg and Strix halo which is designed for light laptops as well can go up to 125W. ZenbookS16 is so thin that one of the review I read complained they had issue with one of the USB-C ports barely fitting in the chassis.
Yes, there are a 16" ProArt and a 13,3" ProArt and both have better performance than the 16" Zenbook S.Umm, the ZenbookS and ProArt are 2 different laptops?
No. So many classic cores would be nothing but a waste in a laptop chip = in this small power envelope = with this little budget for number of cores which simultaneously clock very fast.8+4 setup would have been perfect. 8 Zen5 cluster is used for maximum performance (both ST and MT), while the 4 Zen5C cluster would be used as a low power island for power efficiency.