Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[Bigos]

How does Zen 3 IPC gain have anything to do with Zen 5 uarch? Can you discuss it somewhere else or do we have this thread blocked again?

 

[Abwx]

How does Zen 3 IPC gain have anything to do with Zen 5 uarch? Can you discuss it somewhere else or do we have this thread blocked again?

It went there because RGT stated that Zen 5 would provide better IPC improvement comparatively to Zen 4 than what was brought by Zen 3 comparatively to Zen 2.

So i provided Zen 3 numbers to have an idea of what is supposed to be bested, but as usual there s some people with few knowledge on the matter dismissing those numbers for whatever reason, likely that it s some kind of trolling, hence the lengthy debate...

 

[eek2121]

They didn't, it's just physdes flexing.

How many times do I have to tell everyone that AMD does a proper tock every other gen (they're odd-numbered) and every even is iterative.

Regarding tick-tock, This is simply not true.

Zen1, Zen+, Zen 2, and all variants = family 17h

Zen 3, Zen3+, Zen 4, and all variants are 19h

Zen 5 is 1Ah.

Of these, Zen 3 was considered a ‘tock’ due to a block level rebuild of the silicon which likely changed enough in terms of errata and performance characteristics it could be considered breaking.

Zen 5 supposedly is the next rebuild.

Oh and while the core in Zen 4 has evolved, it is still a direct descendant of the core in Zen 1, sharing many similarities, limitations, pitfalls, etc. It remains to be seen if this changes with Zen 5 or if it truly is a new design.

 

[Exist50]

You are lying here, dunno why you re acting like this.

When I said, "same methodology", I mean humoring the idea that "MT IPC" is an actual metric that can be measured in the way AMD marketing presented. They just used a different set of tests for the sake of comparison. That's not some standard part of their reviews, is the point.

Anyway, going back to the original purpose of assessing rumor mongers, there's any number of things from their history you can point to to know they're making it all up. They take advantage of you giving them this benefit of the doubt for views (money), even if they have to lie to your face to do so. It's just not worth anyone's time to take such claims seriously.

 

[Abwx]

When I said, "same methodology", I mean humoring the idea that "MT IPC" is an actual metric that can be measured in the way AMD marketing presented. They just used a different set of tests for the sake of comparison. That's not some standard part of their reviews, is the point.

I thought that you noticed that Computerbase metrics ,separating ST and MT numbers as well as not using games, are completely different from AMD s (FTR they did an average for games starting with Zen 4) but since you didnt notice there s nothing i can add on the subject.

Anyway, going back to the original purpose of assessing rumor mongers, there's any number of things from their history you can point to to know they're making it all up. They take advantage of you giving them this benefit of the doubt for views (money), even if they have to lie to your face to do so. It's just not worth anyone's time to take such claims seriously.

If we look at Zen 4 improvements most significant contributions in order of importance come from the front end, although it was unchanged globally, LSU and then branch prédiction, exe engine and cache improvements are the two least meaningfull in the list of contributions.

Now if we look at Zen 5 stated improvements AMD pointed a re-pipelined front end and a wider issue, the latter requiring forcibly a better branch prédiction as well as an improved LSU to cope with the augmented scheduling of instructions.

So they are reworking parts that are instrumental to extract more IPC, wich tell us that a significantly bigger improvement than what was brought by Zen 4 is more than likely.

 

[Exist50]

I thought that you noticed that Computerbase metrics ,separating ST and MT numbers as well as not using games, are completely different from AMD

Again, copying the methodology, but different test suite, hence different results.

So they are reworking parts that are instrumental to extract more IPC, wich tell us that a significantly bigger improvement than what was brought by Zen 4 is more than likely.

Yes, Zen 5 in all likelihood will be a bigger IPC jump than Zen 4. Overall performance, however, might not be, if they don't get a meaningful frequency boost as some are alleging. Would fit better into the pattern of Zen 3, which makes sense given that that was also a new architecture, though by a different team, iirc. Clearly they originally wanted to use N3.

 

[Abwx]

Again, copying the methodology, but different test suite, hence different results.

Rather than aknowledging that you were wrong you keep being in denial, different methodologies hence different results, theres s no separation of ST, MT and games in AMD s slide, while Computerbase separate ST, MT and games and provide averages for each of these cases, there s really no worst blind that the one that keep his eyes closed purpotedly...

Yes, Zen 5 in all likelihood will be a bigger IPC jump than Zen 4. Overall performance, however, might not be, if they don't get a meaningful frequency boost as some are alleging. Would fit better into the pattern of Zen 3, which makes sense given that that was also a new architecture, though by a different team, iirc. Clearly they originally wanted to use N3.

There will be a significant uplift because they ll use 4nm instead of 5nm, wich will give a lttle room to improve perf, to wich will be added some significant IPC uplift, they know well for ages that they couldnt rely on a vastly better process for this gen, hence they logically did put much more efforts in IPC.

I guess that you re not trying to have a logical reasoning but rather are hoping that the progress will be meaningfull to better help intel quiting the rear view mirror, unfortunaly that likely wont happen because Zen 5 look like a big push architecturally wise, bigger than all previous iterations of Zen.

 

[HurleyBird]

Regarding tick-tock, This is simply not true.

Zen1, Zen+, Zen 2, and all variants = family 17h

Zen 3, Zen3+, Zen 4, and all variants are 19h

Zen 5 is 1Ah.

Obviously @adroc_thurston, like most of us, was not counting + variants as generations.

 

[Exist50]

Rather than aknowledging that you were wrong you keep being in denial, different methodologies hence different results, theres s no separation of ST, MT and games in AMD s slide

You should reread my comments, because I addressed all of that several times now. I'll ignore the rest of your attempted provocation.

There will be a significant uplift because they ll use 4nm instead of 5nm, wich will give a lttle room to improve perf

4nm does not give a significant improvement vs 5nm, and that's even assuming all these design/architecture changes have no impact on the critical path, which is unlikely.

they know well for ages that they couldnt rely on a vastly better process for this gen

When originally planning for the core, they most likely assumed a healthy N3 with noticeable improvements over 5nm. But TSMC slipped, and so they had to retarget N4 instead.

 

[Abwx]

You should reread my comments, because I addressed all of that several times now. I'll ignore the rest of your attempted provocation.

Anything that prove you wrong is indeed provocation, i produced hard numbers while, as usual, you are left manipulating numberless and hollow sentences.

4nm does not give a significant improvement vs 5nm, and that's even assuming all these design/architecture changes have no impact on the critical path, which is unlikely.

4nm doesnt need to bring much improvement, just enough to keep clocks at say 95% and get the same power given that this latter will be increased due to bigger uarch and higher throughput/Hz, 0.95X the frequency allow for 12-13% lower power, to wich will be added the small improvement over 5nm.

This will end at 0.8x the power and would allow same power at at better than 1.25x higher throughput assuming a theorical 25% better IPC in MT.

When originally planning for the core, they most likely assumed a healthy N3 with noticeable improvements over 5nm. But TSMC slipped, and so they had to retarget N4 instead.

There s different flavours of N4, some that have efficency close enough to N3, FI N4P has 6% better perf at isowatt than N4, this allow to reduce power by about 15% at isofrequency comparatively to N4.

Relatively to N5, wich interest us most, it allow 11% better perf/isowatt or 24% lower power at isoperf, there s enough room for Zen 5 to have 31% better perf at same TDP than Zen 4.

Guess that you did a mental build up to find all possiblities that could make Zen 5 being bottlenecked by whatever suits your hopes, but those numbers just crumble your house of cards theories...

 

[Exist50]

N3, FI N4P has 6% better perf at isowatt than N4, this allow to reduce power by about 15% at isofrequency comparatively to N4.

To just point out the most glaring of many inaccuracies here, 6% better perf/watt means ~6% lower power at iso-frequency, not 15%. Fabs would call the other metric performance. But if I have to once again repeat common knowledge, I think this conversation no longer has value.

 

[Abwx]

To just point out the most glaring of many inaccuracies here, 6% better perf/watt means ~6% lower power at iso-frequency, not 15%. Fabs would call the other metric performance. But if I have to once again repeat common knowledge, I think this conversation no longer has value.

That s 6% better perf (not perf/watt) from N4 to N4P wich mean 6% higher frequency at same power, and since TSMC s process scale at P = F^2.6 slope it means that at same frequency power is 1/1.06^2.6, that is 0.86x the power.

From N5 to N4P, since Zen 4 use the former, perf is 11% better at same power, this means that at same frequency power is 1/1.11^2.6 = 0.76x.

The only inaccuracies are from the one that do understand jack to semiconductors physics, i understand better why you thought that Zen 5 wouldnt perform much better...

 

[Doug S]

That s 6% better perf (not perf/watt) from N4 to N4P wich mean 6% higher frequency at same power, and since TSMC s process scale at P = F^2.6 slope it means that at same frequency power is 1/1.06^2.6, that is 0.86x the power.

From N5 to N4P, since Zen 4 use the former, perf is 11% better at same power, this means that at same frequency power is 1/1.11^2.6 = 0.76x.

The only accuracies are from the one that do understand jack to semiconductors physics, i understand better why you thought that Zen 5 wouldnt perform much better...

Where did you get the information for the exponential function of TSMC's process scaling? Have they actually made that public or are you relying on reverse engineering other data?

 

[Abwx]

Where did you get the information for the exponential function of TSMC's process scaling? Have they actually made that public or are you relying on reverse engineering other data?

It can be easily interpolated using frequency/voltage curves of AMD CPUs that you can find here and there, of course this apply not to extreme frequencies where the curve is of cubic shape and even bi-quadratic in the last drops of frequency.

FTR by physical principle a theorical perfect mosfet has a quadratic power/frequency curve, meaning that power increase as a square of frequency, in practice such a perfect behaviour is not achieved, Intel often managed to have a good behaviour with a 2.2-2.3 exponent while TSMC s is closer to 2.6.

But that s not the only parameter at play, TSMC s lower transconductance (wich mean a steeper curve) is compensated by lower capacitance, so at average frequencies their process can have better perf/watt despite slightly higher voltage, the curve is steeper but is translated lower in the power/frequency graph.

 

[LightningZ71]

With AMD essentially stating that they aren't chasing Intel's strategy of shoveling small cores into a processor and, if rumor is to be believed, going so far as to eliminate SMT from at least some future big cores, they will be hard pressed to keep up with MT throughput unless they find a way to realize significant gains in other areas. It seems to me that they will gain significantly in MT performance on the back of two things for Zen5. With the widening of the core, there should be greater opportunities to exploit unused processor resources to enhance SMT throughput. Improving their SMT performance by more than a few percent can certainly make up a lot of ground in MT. In addition, the increased efficiency of N4 in whatever flavor AMD employs it should allow for higher all-core loaded frequencies, or at least effective work done.

If you include that they expect overall IPC for their cores to go up, then their SMT throughput should show a notable rise in general. So, while we believe that Raptor Lake refresh won't see a notable improvement in the E cores, Zen5 should see improvements against their effects.

I don't think that Zen5 suffers against Intel's 15th gen parts in either ST or MT performance.

 

[Exist50]

With AMD essentially stating that they aren't chasing Intel's strategy of shoveling small cores into a processor

If you look at just AMD's statements on the matter, and ignore the internet commentary, they've said nothing bad about hybrid. Around ADL's launch, they basically just said they would wait till the software ecosystem had adapted. I think it's pretty likely that they will eventually do an 8+16 flagship SKU. The biggest problem is that their small core development is serialized behind the big core, and the desktop chips are the first things they launch on a new arch. They will need to shift to doing those in parallel, but iirc, there were already some rumors along those lines.

 

[turtile]

AMD didn't say that they won't add small cores. They said that they will not mix cores that need software to run differently on each core. Papermaster also said that the reason they are not going over 16 cores is because the memory can't keep up in a dual-channel format.

 

[Thibsie]

AMD didn't say that they won't add small cores. They said that they will not mix cores that need software to run differently on each core. Papermaster also said that the reason they are not going over 16 cores is because the memory can't keep up in a dual-channel format.

That's what I remember too.
They won't do small cores that introduce ISA differences between big and small cores.
Thay might just do as now : see Bergamo or introduce separate small cores but they won't have ISA differences, at least handled (really, not handled at all: just disabled) the way Intel did.

 

[Joe NYC]

If you look at just AMD's statements on the matter, and ignore the internet commentary, they've said nothing bad about hybrid. Around ADL's launch, they basically just said they would wait till the software ecosystem had adapted. I think it's pretty likely that they will eventually do an 8+16 flagship SKU. The biggest problem is that their small core development is serialized behind the big core, and the desktop chips are the first things they launch on a new arch. They will need to shift to doing those in parallel, but iirc, there were already some rumors along those lines.

Just FYI, MLID showed some road map where Turin Dense came ahead of regular Turin.

It is not clear how it translates to desktop release schedule, but it seems that the dense CCD is not going to be lagging behind regular CCDs by very long.

 

[eek2121]

AMD didn't say that they won't add small cores. They said that they will not mix cores that need software to run differently on each core. Papermaster also said that the reason they are not going over 16 cores is because the memory can't keep up in a dual-channel format.

I don’t buy that argument about memory bandwidth at all.

Motherboard OEMs are beginning to roll out test BIOS versions with a new AGESA that supports the fastest DDR5 speeds out there. In addition, memory speeds are already significantly faster than what DDR4 is capable of. Intel also has no issues with higher core counts. Finally, who cares if some workloads are limited by bandwidth? The hypothetical 8+16 chip will still be faster.

They could also solve things by moving to a quad channel setup for high end enthusiast offerings.

If they dropped a quad channel board and a 24c CPU that beats up the 7950X many of us would buy it in a heartbeat.

 

[Joe NYC]

I don’t buy that argument about memory bandwidth at all.

Motherboard OEMs are beginning to roll out test BIOS versions with a new AGESA that supports the fastest DDR5 speeds out there. In addition, memory speeds are already significantly faster than what DDR4 is capable of. Intel also has no issues with higher core counts. Finally, who cares if some workloads are limited by bandwidth? The hypothetical 8+16 chip will still be faster.

They could also solve things by moving to a quad channel setup for high end enthusiast offerings.

If they dropped a quad channel board and a 24c CPU that beats up the 7950X many of us would buy it in a heartbeat.

Considering where things stand:
- AM5 is dual channel
- Sienna platform is (likely) 6 memory channels
- Strix Halo is 4 internal memory channels

The chances of AMD releasing 4 memory channel socket are near zero.

What could be interesting, if Strix Halo can fit into AM5 socket, would be to have 4 internal memory channels and 2 external.

 

[igor_kavinski]

The chances of AMD releasing 4 memory channel socket are near zero.

Why wouldn't anyone at AMD see an opportunity in that? Enthusiasts already pay quite a bit for the AM5 flagship CPU/mobo combo so they may not mind paying a bit more for a higher end chipset with quad channel RAM. AMD can keep 6,8 and 12 channel RAM for workstation and servers.

 

[Exist50]

Why wouldn't anyone at AMD see an opportunity in that? Enthusiasts already pay quite a bit for the AM5 flagship CPU/mobo combo so they may not mind paying a bit more for a higher end chipset with quad channel RAM. AMD can keep 6,8 and 12 channel RAM for workstation and servers.

It would be a large platform investment for a very small volume. Socket and mobo pricing is extremely sensitive to volume. And of course, you'd need a 4ch die...

 

[igor_kavinski]

It would be a large platform investment for a very small volume.

Volume could increase depending on how tangible the gains are.

 

[HurleyBird]

We should have stuck with triple channel after Nehalem.