Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[Nothingness]

Since you post there you should ask him why in the ST tests he removed CB R15 to replace it with CB R20 while there s already CB R23,

Why not R24?

and why he s using POVRAY 3.7 wich is known to give an unfair advantage to Intel since it doesnt enable AVX2 for AMD.

Povray dev has been dead for years (though looking at the sources it seems they added proper CPU detection after 3.7). Definitely a poor choice and redundant with CB. IMHO Blender would be a better choice if he insists on having an open source renderer.

 

[Abwx]

Sorry, in which test is that? I can't find it.

Their single core perf test, check here, there s the MT score graph followed by the ST core perf graph :

Intel Core i9-14900KS im Test: Anwendungs-Benchmarks, Leistungsaufnahme & Temperatur

Intel Core i9-14900KS im Test: Anwendungs-Benchmarks, Leistungsaufnahme & Temperatur / Testsystem und Testmethodik für Anwendungen

www.computerbase.de

 

[poke01]

Reviewers should really be using Cinebench 2024.

 

[Philste]

Their single core perf test, check here, there s the MT score graph followed by the ST core perf graph :

Aaah ok. Yeah, CB will use completely new Parcours starting with ZEN5. Both for Applications and Gaming. Their Application Parcour has always been criticised for being too much of the same in recent years.

 

[yuri69]

the Delay was the right thing to do.

1-2 weeks to fix the firmware/AGESA? This seems like a bad joke. Rushing last minute fixes often leads to breaking stuff even more (due skipping a standard validation procedure, etc.).

 

[Abwx]

Why not R24?


Povray dev has been dead for years (though looking at the sources it seems they added proper CPU detection after 3.7). Definitely a poor choice and redundant with CB. IMHO Blender would be a better choice if he insists on having an open source renderer.

Member MarkPost made the demonstration in this very forum when it comes to Povray, he recomplied the code to enable AVX2 for AMD and he found that Computerbase numbers where lower in both ST and FP, actually Zen 4 is faster than RPL in both ST and MT, IIRC the ST score he found is about 900 while at Computerbase it s 769, so that s a big bias.

Reviewers should really be using Cinebench 2024.

With CB R20 Intel gained 8-10% in respect of AMD comparatively to CB R15, and in CB R23 they gained another 1-2%, guess that it s easier to "improve" the bench than a CPU when it comes to "increase" IPC.

Aaah ok. Yeah, CB will use completely new Parcours starting with ZEN5. Both for Applications and Gaming. Their Application Parcour has always been criticised for being too much of the same in recent years.

I wonder what is this new parcour, they used one where RPL has as much as 60% better perf than the 7950X in some MT "bench", hope they wont come with such discrepancies.

Edit : Their alternative parcour can be found here, there s several dubbious tests :

Core i9-13900K, i7-13700K & i5-13600K: Gaming-Könige im Test: Benchmarks in Apps

Intel Raptor Lake im Test: Benchmarks in Apps / So wurde getestet / Leistung in Single-Core-Lasten (klassisch)

www.computerbase.de

 

[Philste]

Edit : Their alternative parcour can be found here, there s several dubbious tests :

That is the Raptor Lake release test from 2022. Yeah, they tried a new one there, but I haven't seen it ever since. All I can say is that they said they will do completely new parcours starting with ZEN5. Go on the site on Wednesday and then you can see how "dubious" they are.

 

[Abwx]

That is the Raptor Lake release test from 2022. Yeah, they tried a new one there, but I haven't seen it ever since. All I can say is that they said they will do completely new parcours starting with ZEN5. Go on the site on Wednesday and then you can see how "dubious" they are.

Their ST test is dubbious, so it s not like they cant do any wrong, may i remind you that at the time Volker added the first version of 3DPM that is known to be infamously tanking AMD s CPUs perfs, yet he surely noticed that the scores were weird and still he used it as metric for both ST and MT tests, and at the time he was also using 3D Euler despite this software editor explicitely stating in its site that it was voluntarly crippling AMD CPUs.

 

[exquisitechar]

Aaah ok. Yeah, CB will use completely new Parcours starting with ZEN5. Both for Applications and Gaming. Their Application Parcour has always been criticised for being too much of the same in recent years.

Good, it's about time. CB is, overall, a solid outlet, but their ST benchmark suite has been a total disaster for years.

 

[static shock]

Seeing Strix Halo construction.... could be the GPU the next big thing to be intergraded to the CPU?

 

[igor_kavinski]

Average 18% performance uplift at just 2% power increase in SMT on Zen 5/5c: https://www.phoronix.com/review/amd-ryzen-zen5-smt

 

[techjunkie123]

Average 18% performance uplift at just 2% power increase in SMT on Zen 5/5c: https://www.phoronix.com/review/amd-ryzen-zen5-smt

Ehh it's a comparison of SMT on vs off. Of course nice performance gains.

Looks like power limits are the same in both so perf/w is not necessarily accurate because clocks are likely higher without smt. Difference could've been larger if clocks were the same.

 

[JustViewing]

Average 18% performance uplift at just 2% power increase in SMT on Zen 5/5c: https://www.phoronix.com/review/amd-ryzen-zen5-smt

some benches, nearly 40% . Seems fat core has its benefits. Not sure how the Zen4 HT performs in same tests.

 

[Nothingness]

Average 18% performance uplift at just 2% power increase in SMT on Zen 5/5c: https://www.phoronix.com/review/amd-ryzen-zen5-smt

It would have been interesting to include more single thread benchmarks to see if there was some impact.

 

[CouncilorIrissa]

It would have been interesting to include more single thread benchmarks to see if there was some impact.

Yeah, I'd like to see some browser benchmarks.
One interesting caveat is that he disables the SMT via `nosmt` kernel parameter. I'm wondering whether disabling SMT in BIOS and on kernel-level is any different.

Some say that there is a difference, but I'm not sure how accurate the answer is:

Hyper Threading: nosmt in grub configuration

Currently, I have running Debian 12 instance on dedicate CPU cloud environment. It has 2 cores, 4 threads. It is not impossible to turn off hyper threading via BIOS settings. I found possibility to

stackoverflow.com

It's especially interesting in the context of Zen 5 because decoders are statically partitioned with SMT apparently.

 

[Nothingness]

Yeah, I'd like to see some browser benchmarks.
One interesting caveat is that he disables the SMT via `nosmt` kernel parameter. I'm wondering whether disabling SMT in BIOS and on kernel-level is any different.

Some say that there is a difference, but I'm not sure how accurate the answer is:

Hyper Threading: nosmt in grub configuration

Currently, I have running Debian 12 instance on dedicate CPU cloud environment. It has 2 cores, 4 threads. It is not impossible to turn off hyper threading via BIOS settings. I found possibility to

stackoverflow.com

It's especially interesting in the context of Zen 5 because decoders are statically partitioned with SMT apparently.

Ha I missed that he did that with a kernel parameter. Then it indeed wouldn't change ST results. I hope we'll see some reviewers testing it by disabling HT in the BIOS (and hoping it really disables HT...).

 

[DavidC1]

I am afraid it's about bad marketing message and miscommunication. The materials were mentioning that decoders are statically partitioned in SMT mode.

I don't know if it's just bad marketing.

The design teams aim for a goal and quite occasionally they miss. Which is why you actually test it rather than believe what even the engineers themselves say. I've seen it many times. They claim something and the benches show something off.

Intel for example didn't live up to their L1 cache bandwidth if you computed it using the Load/Store values. It was only fairly recently it did. Rather than being 32 bytes it was 28 bytes or 26 bytes.

If David Huang's tests are true, then it has worst decoder capability than Tremont, the E core chip from 4 years ago. And Gracemont and Tremont has improved greatly each generation, to the point where the clusters rarely ever not execute in parallel. This feeds into my belief that BOTH P core teams are in need of a big change for the better.

 

[Josh128]

Supposedly review embargo lift is Aug 7 for the single CCD parts, 14th for dual CCD.

 

[MS_AT]

I don't know if it's just bad marketing.

The design teams aim for a goal and quite occasionally they miss. Which is why you actually test it rather than believe what even the engineers themselves say. I've seen it many times. They claim something and the benches show something off.

Intel for example didn't live up to their L1 cache bandwidth if you computed it using the Load/Store values. It was only fairly recently it did. Rather than being 32 bytes it was 28 bytes or 26 bytes.

If David Huang's tests are true, then it has worst decoder capability than Tremont, the E core chip from 4 years ago. And Gracemont and Tremont has improved greatly each generation, to the point where the clusters rarely ever not execute in parallel. This feeds into my belief that BOTH P core teams are in need of a big change for the better.

I am afraid that this is a bit too dramatic. If indeed decoders are statically partitioned then each thread will have the same decoding capability that whole Zen4 core had before it. Therefore it's net improvement, and people here were underlining that what's important is the real performance you get. And this will boost the real performance of the whole system as there is often something else running.

About Mont cores, they don't have SMT/HT so it's a bit different thing. Might be that arbitration between HW contexts in SMT mode was too difficult and doing static partitioning gave better overall results.

So while 8 wide decoder probably would do better in ST benchmarks, AMD tried to do something else here. Maybe not novel but they are at least experimenting with different solutions.

We will have reviews go out in few days, we will see how AMD team did.

 

[igor_kavinski]

9600X vs. 7600X on the same mobo: https://browser.geekbench.com/v6/cpu/compare/7182575?baseline=7181563

Looks like nothing to write home about

 

[exquisitechar]

9600X vs. 7600X on the same mobo: https://browser.geekbench.com/v6/cpu/compare/7182575?baseline=7181563

Looks like nothing to write home about

The Zen5% jokes weren't that far off. The reality is Zen10%.

 

[Markfw]

9600X vs. 7600X on the same mobo: https://browser.geekbench.com/v6/cpu/compare/7182575?baseline=7181563

Looks like nothing to write home about

geekbench. Need I say more.

 

[ErichZannMusician]

geekbench. Need I say more.

ST. Look at ST.

 

[Kaffeekenan]

9600X vs. 7600X on the same mobo: https://browser.geekbench.com/v6/cpu/compare/7182575?baseline=7181563

Looks like nothing to write home about

But 3,9 vs. 4,7 GHz or am I blind?

EDIT: Apparently I am blind.

 

[ErichZannMusician]

But 3,9 vs. 4,7 GHz or am I blind?

It's worse - 5.2 GHz for the 7600X vs 5.4 GHz for the 9600X.