Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[MS_AT]

The Core Parking seems to me more like a band aid to the problem [we know if we let threads across CCD communicate it will tank performance] rather than reason for the problem. I mean they did not bother to update 7900x or 7950x even though they could, but probably there it wasn't worth it when they were releasing x3d. That would not hurt x3d sales but could have been used as nice marketing trick. Anyway this is all speculation on my part.

But yes, after decoder mystery got solved, we got new one. Zen 5 the gift that keeps on giving

 

[Det0x]

Anyone know of a good program to measure core to core latency ?
I tried MicroBenchX.C2CLatency and and it spat out this

When i tried to save the data window closed, and i'm not running that again (~20min runtime)
If im reading it right, its ~20ns inter CCD and up in the 150-180ns range for cross ccd (?)

 

[yuri69]

Actually it is worse.
AMD basically stopped shipping iterations of Bulldozer for DIY desktop. But they really did polish that turd almost every year through 2015! Zen 5 won't be getting that yearly treatment.

Yea, this is depressing.

AMD pushed a Piledriver-based APU in... 7 months after Bulldozer. Meanwhile Zen 6 is coming in 2026/2027.

 

[Hitman928]

I really doubt that. I mean I’m not an expert, but it it’s been shown in other reviews it takes on the order of ~ 1 ms to hit boost frequency

~ 100 ns is on the order of RAM access latency, I can’t imagine it coming out of any kind of sleep anywhere near that fast. The voltage regulation, everything else will respond on timescales much longer than that. Just based on my intuition and respect for orders of magnitude I don’t think there can be a software (Windows driver) reason to explain the extra 120 ns. Microcode, maybe.

Are you sure it takes that long and is not just the limit of the monitoring method?

 

[Tup3x]

Whelp, we have confirmation the review guide was a mess. They had to message reviewers later and tell them the dual CCD parts need special attention. You can click on the image to open timestamped GN 9950X review.

View attachment 105294

This really shouldn't be necessary. They really need to change this.

 

[Hitman928]

Anyone know of a good program to measure core to core latency ?
I tried MicroBenchX.C2CLatency and and it spat out this
View attachment 105318
When i tried to save the data window closed, and i'm not running that again (~20min runtime)
If im reading it right, its ~20ns inter CCD and up in the 150-180ns range for cross ccd (?)

Try this. https://github.com/nviennot/core-to-core-latency/releases/tag/v1.0.0

Edit: May need to run as admin.

 

[biostud]

So are we still expecting X3D in September? Mid or end of? Based on what?

Any chance it will magically be able to save Zen5?

Only if this redesigned core somehow can run @5.4-5.5Ghz with 3D cache.

 

[sl0519]

Is there a detailed description anywhere of what we are seeing in this graph and how it was produced?

I hope the regression versus Zen 4 < 125 W is an artifact of the particular desktop setup. (Because Turin vs. Genoa eventually needs to have a very different outcome than this one...)

[It's not a rehash of the older 9950X *ES* measurements, is it?]

Cinebench R23 PPT scaling.
Regression in very low wattages are also present in Geekerwan’s Strix Point review if I recall correctly.

*edit: it was Spec2017 that showed regression from Hawk, R23 was still performing better in every ppt.

 

[Josh128]

Actually it is worse.
AMD basically stopped shipping iterations of Bulldozer for DIY desktop. But they really did polish that turd almost every year through 2015! Zen 5 won't be getting that yearly treatment.

Ummm...hate to break it to you but Zen 5 will 100% be getting that "turd polishing" treatment. It is AMDs "new foundation" for x86 CPUs. Zen 6 will take Zen 5 core arch, put on a smaller process, a few various enhancements (possibly with a 16 core CCX per CCD), along with presumably brand new uncore / IOD setup. Then Zen 7 will iterate on what Zen 6 has done. All will use the Zen 5 core.

 

[StefanR5R]

The Core Parking seems to me more like a band aid to the problem

Apparently a poor bandaid just like it has to happen when ISV, OS maker, OEM and CPU maker are not quite getting together for a more targeted implementation. Like assigning CPU affinities to the game process at its startup, maybe.

after decoder mystery got solved

Well, we learned quite a bit more (how it behaves on GNR, whether or not SMT disabled in the BIOS influences its behavior, what the impact in actual workloads is, plus the commentary that moving the various resources between 1T mode to 2T mode is not entirely trivial and has got latencies). There are still more pieces to the puzzle left to discover (or not). Such as why this is counter to what M. Clark said when being interviewed.

 

[gdansk]

Ummm...hate to break it to you but Zen 5 will 100% be getting that "turd polishing" treatment. It is AMDs "new foundation" for x86 CPUs. Zen 6 will take Zen 5 core arch, put on a smaller process, possibly with a 16 core CCX per CCD, along with presumably brand new uncore / IOD setup. Then Zen 7 will iterate on what Zen 6 has done. All will use the Zen 5 core.

Emphasis on yearly treatment.
It's 22 months between iteration for Zen.

 

[StefanR5R]

Cinebench R23 PPT scaling.
Regression in very low wattages are also present in Geekerwan’s Strix Point review if I recall correctly.

Any info which allows for an estimation of core/uncore power split?

 

[sl0519]

Any info which allows for an estimation of core/uncore power split?

Not sure. Here’s the source of the video.
https://www.bilibili.com/video/BV15T421r7jk/

It’ll be on YT sooner or later. See if auto translate will be available.

 

[Det0x]

Try this. https://github.com/nviennot/core-to-core-latency/releases/tag/v1.0.0

Edit: May need to run as admin.

thanks, that worked out well 👍

 

[Hitman928]

thanks, that worked out well 👍
View attachment 105320

Looks very similar to Anandtech's results.

 

[sl0519]

Only if this redesigned core somehow can run @5.4-5.5Ghz with 3D cache.

If they somehow manage to hit clock parity with X variant, I genuinely think there’s no point for the existence of lower end X variants. People who are into productivity tasks naturally gravitate toward R9s anyway.

 

[MS_AT]

thanks, that worked out well 👍

I guess you are not using this fancy driver so we can exclude this as a cause, therefore it's a band aid and they botched something it seems...

 

[Hitman928]

I guess you are not using this fancy driver so we can exclude this as a cause, therefore it's a band aid and they botched something it seems...

I think the behavior is inherent to the CPU when there is low activity, the driver is for the OS to schedule only on the active CCD according to whatever requirements it has for doing so.

 

[Det0x]

I guess you are not using this fancy driver so we can exclude this as a cause, therefore it's a band aid and they botched something it seems...

That fancy driver as you put it is not a fix, its a work-around trying to mitigate the problem
That's at least my take if i understand it correctly

 

[exitorious]

thanks, that worked out well 👍
View attachment 105320

7950x3d for comparison.

 

[Det0x]

7950x3d for comparison.

Did you use this cmd to run ? Or just make the window larger so its easier to read👍
core-to-core-latency 5000 --csv > output.csv

 

[Hitman928]

That fancy driver as you put it is not a fix, its a work-around trying to mitigate the problem

Yeah, that's kind of how I see it. I think this behavior was intentional to lower the power consumption of the overall package when only needing a few cores. The driver is there to try and stop the OS from using both CCDs when only 1 is needed, to avoid having to wake up the other cores and suffer a power and performance penalty. Though, it seems to be mostly concerned with gaming loads, or whatever it sees as a gaming load.

 

[exitorious]

Did you use this cmd to run ?
core-to-core-latency 5000 --csv > output.csv

Yes, I just copied what you did. Didn't output it to a csv file though. Heres one where I did.

 

[MS_AT]

That fancy driver as you put it is not a fix, its a work-around trying to mitigate the problem
That's at least my take if i understand it correctly

Yes I agree. I simply meant that some people thought driver is the reason for high latency and since you are not using it, we know it's not.

Yeah, that's kind of how I see it. I think this behavior was intentional to lower the power consumption of the overall package when only needing a few cores. The driver is there to try and stop the OS from using both CCDs when only 1 is needed, to avoid having to wake up the other cores and suffer a power and performance penalty. Though, it seems to be mostly concerned with gaming loads, or whatever it sees as a gaming load.

That would make sense if this was burst behaviour but I guess you can keep all cores active [disable power saving options in the bios should prevent lower power states? maybe something in the windows power planes] and the picture wouldn't be changed fundamentally. Might be that test itself is enough to keep the cores awake.

 

[Josh128]

Almost certainly the "core parking" thing they are implementing during gaming is required because of the increased cross CCD latency, not the cause of it. With it over doubling from Zen 4, any game threads that crept onto CCD 1 could bring a massive drop in performance, so they were basically forced to do it or risk Bulldozer'esque gaming regressions.

Also, regarding X3D, the chance that they launch with a greater than 5.3G boost is almost zero. In fact, I'd be more willing to bet that it might top out at 5.2G out of the box and they "will allow the user" to try to OC to obtain more at their own peril. Think about it, Zen 5 barely holds its 1T boost in something like R23 without a delicate X3D chip stacked on top of it, why in the world would we expect significantly higher boosts than Zen 4 X3D?