Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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mostwanted002

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Mahboi

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CouncilorIrissa

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pity it wasn´t ZEN3 team ...
They're supposedly working on Zen 7. The odd-numbered cores are new designs, even ones are iterations.
However, AMD did not do this. In our interviews with AMD’s senior staff, we have known that AMD has two independent CPU core design teams that aim to leapfrog each other as they build newer, high performance cores. Zen 1 and Zen 2 were products from the first core design team, and now Zen 3 is the product from the second design team. Naturally we then expect Zen 4 to be the next generation of Zen 3, with ‘the low hanging fruit’ taken care of.
 

Mahboi

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He’s worse than the British tabloids lol

Is the meme actually accurate?
pity it wasn´t ZEN3 team ...
The Zen 2 team did an even greater job than the Zen 3 team.
However it's not unthinkable that Zen 5 did suffer from a lot of unexpected problems. I keep reading that it's "FP oriented", I'm still not quite sure of it. It feels like the INT capacity is as good as it can get compute wise. I was talking with Alexander Yee(Mysticial, Y-cruncher dev) earlier, and his article was pretty clear: if Zen 5 wants to fully feed its AVX 512 pipelines, it wants DDR5 20000, not DDR5 6000. Although scalar/INT doesn't need nearly as much throughput, it seems that our memory bw and general memory problems are getting much, much worse. I'm just not sure how can cache, local memory or a (much) better memctrl can get the job done. Zen 5 even has 6 INT ALUs and apparently can't even use them all at the same time. So for all I know it could be that it's not even possible to feed it enough data between instructions to use all 6. I don't know just how undersized the INT is, on the contrary I get the vibe that its sized a little above what it needs, but membw/memlat just don't feed it hard enough.
 
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marees

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They're supposedly working on Zen 7. The odd-numbered cores are new designs, even ones are iterations.

However, AMD did not do this. In our interviews with AMD’s senior staff, we have known that AMD has two independent CPU core design teams that aim to leapfrog each other as they build newer, high performance cores. Zen 1 and Zen 2 were products from the first core design team, and now Zen 3 is the product from the second design team. Naturally we then expect Zen 4 to be the next generation of Zen 3, with ‘the low hanging fruit’ taken care of.
Did I understand this correctly ?

Team-1: zen1, zen2, zen5, zen6
Team-2: zen3, zen4, zen7?, zen8?

So zen-6 will also be meh (other than upgrade to 3nm?)
 

mostwanted002

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Did I understand this correctly ?

Team-1: zen1, zen2, zen5, zen6
Team-2: zen3, zen4, zen7?, zen8?
Team one odd. Team two even.

So,

Team-1: zen1, zen3, zen5,zen7
Team-2: zen2, zen4, zen6, zen8

Zen 2 team can only mess up Zen 6 if they are supposed to be bad but they did a nice job with Zen 4. That's why MLID is so dumb. Doesn't even try to use common sense before posting rumors (or making them up).
 

CouncilorIrissa

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Team one odd. Team two even.

So,

Team-1: zen1, zen3, zen5,zen7
Team-2: zen2, zen4, zen6, zen8

Zen 2 team can only mess up Zen 6 if they are supposed to be bad but they did a nice job with Zen 4. That's why MLID is so dumb. Doesn't even try to use common sense before posting rumors (or making them up).
No, even gens -- leveraged cores -- are done by the same team that created the initial design in the previous gen.
 

Josh128

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Rumor mill says drama on zen5 design lead to problems with software etc..

Zen 5 clearly has issues. Could be architectural, could be microcode/software, in reality, its probably is both. Tom is claiming this probably could have been avoided with couple month delay, but its very likely that an extra two months would not help. Im thinking it would not, and the reason Im thinking that is if they really believed it would, they would have done it. Anyone expecting miracles from a new AGESA or chipset drivers needs to temper their expectations. I dont believe the CCD to CCD latency issues are fixable. That is a gigantic issue, big enough that if it was something they reasonably thought could be fixed with microcode, they would have pushed back the launch and done it.

Its very possible that current Zen 5 performance and characteristics is just what they have, and they were faced with two options: Either launch it as is, or dont launch it at all, and they chose the former. To his credit, Tom DID leak prior to the launch that there was some real trouble encounted in the Zen 5 design, and it does appear looking from the outside that is very plausible.
 

yottabit

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Zen 5 clearly has issues. Could be architectural, could be microcode/software, in reality, its probably is both. Tom is claiming this probably could have been avoided with couple month delay, but its very likely that an extra two months would not help. Im thinking it would not, and the reason Im thinking that is if they really believed it would, they would have done it. Anyone expecting miracles from a new AGESA or chipset drivers needs to temper their expectations. I dont believe the CCD to CCD latency issues are fixable. That is a gigantic issue, big enough that if it was something they reasonably thought could be fixed with microcode, they would have pushed back the launch and done it.

Its very possible that current Zen 5 performance and characteristics is just what they have, and they were faced with two options: Either launch it as is, or dont launch it at all, and they chose the former. To his credit, Tom DID leak prior to the launch that there was some real trouble encounted in the Zen 5 design, and it does appear looking from the outside that is very plausible.
Surely AMD will make up for it this time around by giving us affordable Zen5 Threadripper with Turin-based IOD..... Surely....
 
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