Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[igor_kavinski]

I kinda feel like throwing a hard question: what can microcode do? How much can microcode tweak/control in a modern CPU?

I think the factory programmed v/f curve of the CPU is read by the microcode and maybe preventing mobos from torturing the CPU unless a certain bit is enabled which probably voids warranty. It can also block instructions or entire CPU blocks (e.g. AVX-512). Not sure about other logic present in microcode.

 

[SK10H]

Zen 5 clearly has issues. Could be architectural, could be microcode/software, in reality, its probably is both. Tom is claiming this probably could have been avoided with couple month delay, but its very likely that an extra two months would not help. Im thinking it would not, and the reason Im thinking that is if they really believed it would, they would have done it. Anyone expecting miracles from a new AGESA or chipset drivers needs to temper their expectations. I dont believe the CCD to CCD latency issues are fixable. That is a gigantic issue, big enough that if it was something they reasonably thought could be fixed with microcode, they would have pushed back the launch and done it.

Wasn't there rumor in this thread way back claiming the current Zen5 A0 stepping was available already internally in early 2023?

 

[CouncilorIrissa]

Wasn't there rumor in this thread way back claiming the current Zen5 A0 stepping was available already internally in early 2023?

Retail GNR is B0.

 

[adroc_thurston]

Few examples

You do see that the 9900X (dual-CCD part) is topping the PTS charts?

 

[csbin]

AVX512 It doesn't help.

https://twitter.com/x/status/1824057613434434042

 

[Markfw]

You do see that the 9900X (dual-CCD part) is topping the PTS charts?

PTS charts ????

 

[Timmah!]

PTS charts ????

i am trying to figure connection between 9900x and post traumatic stress as well.

 

[Gideon]

No, even gens -- leveraged cores -- are done by the same team that created the initial design in the previous gen.

This is the first time I hear about that. I also though the leapfrogging teams leapfrogged every generation

This just seems, odd...

Does this mean Zen 2 could only be started once Zen 1 was completed yet Zen 3 was already started in parallel-way before?

Or do the teams actually work on two designs in parallel? As there is no way you design Zen 4 from ground up in less than 2 years, yet take 4-5 years (that's the norm AFAIK) for Zen 5?

 

[adroc_thurston]

PTS charts ????

Phoronix Test Suite.
Has a lot of filler, but some stuff is very relevant.

 

[leoneazzurro]

I don't know if it has been already reported.

https://twitter.com/x/status/1824038670552473709

 

[DisEnchantment]

This is the first time I hear about that. I also though the leapfrogging teams leapfrogged every generation

This just seems, odd... Zen 2 could only be started once Zen 1 was completed, yet Zen 3 was already started in parallel-way before? And how could zen 3 team release zen 4 so quickly after the first (considering it takes 4-5 years for a design). Are you claiming that the teams actually work on two designs in parallel?

Zen 1 - Mike Clark
Zen 2 - David Suggs
Zen 3 - Marius Evers
Zen 4 - Marius Evers + Kai Troester
Zen 5 - David Suggs

Not sure who is taking Zen 6 (David Suggs left AMD), but Zen 7 is Kai Troester, from what I hear.

The Architecture, RTL and simulation are done way before physical implementation which again is more than a year before launch. I would say Zen 5 design and RTL would have been done by 2022.
So the Zen 5 architecture base and RTL they would reuse to make Zen 6 already, the physical macros are not portable across the nodes anyway.
So at the moment they are already deep in physical implementation for Z6 or about close to done.

The RTL and physical implementation would not have been done by the same people. These are different specialties.

At the moment the designers who worked on Zen 5 have much moved on, what is left are the SoC teams who are putting the macros together.

 

[marees]

This is the first time I hear about that. I also though the leapfrogging teams leapfrogged every generation

This just seems, odd...

Does this mean Zen 2 could only be started once Zen 1 was completed yet Zen 3 was already started in parallel-way before?

Or do the teams actually work on two designs in parallel? As there is no way you design Zen 4 from ground up in less than 2 years, yet take 4-5 years (that's the norm AFAIK) for Zen 5?

It looks like new architecture teams (zen, zen3, zen5, zen?7 etc.) work in parallel it makes sense to give 2 gens to same team as in 1st gen they would target low hanging fruits whereas in next gen they would go for "optimization"

Having said that, this bitching between zen 1/2/5 & zen 3/4 teams seems to be normal politics that wouldn't have been newsworthy if zen5 had done better in client benchmarks

 

[igor_kavinski]

You do see that the 9900X (dual-CCD part) is topping the PTS charts?

Something is clearly wrong. No way the 9900X should have an edge over the 9950X.

Could be the extra traffic for the extra cores is hitting some internal limit.

 

[Hail The Brain Slug]

Something is clearly wrong. No way the 9900X should have an edge over the 9950X.

Could be the extra traffic for the extra cores is hitting some internal limit.

Seems unlikely there would be so much overhead in that hypothetical event as to slow it down to slower than the 7700X. I'd expect it would simply bottleneck it to similar performance, maybe a slight regression from the 9900X.

 

[adroc_thurston]

Something is clearly wrong. No way the 9900X should have an edge over the 9950X.

That's why I don't treat Phoronix as the ultra-gospel. Michael tests so much he rarely checks for outliers.

Could be the extra traffic for the extra cores is hitting some internal limit.

If you're fully membound like y-cruncher, you saturate the thing with ~4c per CCD.

 

[igor_kavinski]

Having said that, this bitching between zen 1/2/5 & zen 3/4 teams seems to be normal politics that wouldn't have been newsworthy if zen5 had done better in client benchmarks

What??? I thought AMD was a chip designer's paradise!

 

[igor_kavinski]

I'd expect it would simply bottleneck it to similar performance, maybe a slight regression from the 9900X.

Yes, that seems reasonable yet that's not happening.

It's like the 9950X is throwing some sort of tantrum when reaching a certain level of workload demand.

"Hey, you want me to work that much for this little power???? I refuse to rise up to the occasion! Next time, give me the power I need to really fly!"

 

[Hitman928]

Yes, that seems reasonable yet that's not happening.

It's like the 9950X is throwing some sort of tantrum when reaching a certain level of workload demand.

"Hey, you want me to work that much for this little power???? I refuse to rise up to the occasion! Next time, give me the power I need to really fly!"

It’s either an issue with the setup or the software is doing something weird with the 32 threads available to it. Phoronix always seems to have weird results due to his testing being completely automated and he doesn’t have the time to actually vet the results. You can find similarly weird results with some of his Intel benchmarks as well, just look at the browser benchmarks. I wouldn’t put too much stock into anomalies in his tests.

 

[Josh128]

You do see that the 9900X (dual-CCD part) is topping the PTS charts?

?? I see that the 9950X is topping the charts, about 10% ahead of the 9900X.

 

[adroc_thurston]

I see that the 9950X is topping the charts, about 10% ahead of the 9900X.

I know reading is Very Hard, but we're talking DB loads.
You know, parallel, cachemem-bound bouncy stuff.
Stuff that (on paper) hates NUCA harder than anything else in the world.

 

[igor_kavinski]

?? I see that the 9950X is topping the charts, about 10% ahead of the 9900X.

Only 12% higher for 33% more threads? Yeah, that's brilliant, ain't it?

7950X is 15.88% faster than 7900X. So Zen 5 regressed. It should have moved the needle up, not down.

 

[Hitman928]

AMD seemingly implements a power saving feature. People see that power saving feature causes additional (most likely expected) latency on a purely synthetic test and freak out about AMD screwing up Zen 5, but there is no real distinguishable difference in actual benchmarks. This forum can be quite a trip, lol.

Only 12% higher for 33% more threads? Yeah, that's brilliant, ain't it?

7950X is 15.88% faster than 7900X. So Zen 5 regressed. It should have moved the needle up, not down.

Ever consider that there may be an actual explanation for it, like it may be running into memory bottlenecks or the previously discussed anomalous results are bringing down the average?

 

[igor_kavinski]

AMD seemingly implements a power saving feature.

AMD shouldn't go around trying to please everyone. There wasn't anything very wrong with Zen 4. They should've improved it further. Right now it looks like a lopsided jumbled mess.

I honestly don't see any point in the dual CCD Zen 5 CPUs unless they fix that latency.

AMD shouldn't go around trying to please everyone.

Case in point: trying to please gamers with the stupid chipset driver/game bar crutch.

Fire the idiot who came up with that. He should know very well that X3D is for gaming, not the dual CCD non-X3D parts.

 

[MarkPost]

Only 12% higher for 33% more threads? Yeah, that's brilliant, ain't it?

7950X is 15.88% faster than 7900X. So Zen 5 regressed. It should have moved the needle up, not down.

well, thats is a complete benchmark suite, not only MT

 

[Hitman928]

AMD shouldn't go around trying to please everyone. There wasn't anything very wrong with Zen 4. They should've improved it further. Right now it looks like a lopsided jumbled mess.

I honestly don't see any point in the dual CCD Zen 5 CPUs unless they fix that latency.

What benchmarks do you see that the extra latency is hurting?