I hope not. Any Zen 5 + launch would delay Zen 6 by at least 8 months. I say screw it, just ride it out with better AGESA/driver updates on X3D stack until Zen 6 on a new platform. Admit failure and move on.If zen 6 is on ddr6 then will there be a zen 5+ on ddr5 & 3nm ?
It was delayed. Yes technically AMD never respected the 18 months target, but 22 months is already effectively beyond 3 months late and with the extra time to actually come out, it's closer to 6 months late. From late september 2022 to mid August 2024.AMDs response to this inquiry will be very telling. I doubt they admit what is really going on. Is it a regression that was necessary due to architectural design choices, a result of halting design at a specific point to meet an internal launch date goal, or is it a silicon level bug that might or might not be fixable by new stepping or microcode.
More and more it looks like desktop Zen 5 should have just been delayed, even if it would be a 6 month plus delay, to get this and other performance anomalies ironed out. I cant wait to see the core latencies on Zen 5C 3nm Turin, which is rumored to have the fabled 16 core CCX.
I hope not. Any Zen 5 + launch would delay Zen 6 by at least 8 months. I say screw it, just ride it out with better AGESA/driver updates on X3D stack until Zen 6 on a new platform. Admit failure and move on.
Another thought which someone probably already posted: what if the inter CCD latency increase was just a conscious tradeoff to save power? I doubt they will come out and just admit that, but it's possible this was a design choice to increase the power budget.
Zen 4 was on N5.If you go through AT articles about TSMC you ll notice that N4P provided only 11% better perf/Watt than N5P wich was used by Zen4, yet AMD managed to increase the perfs by 10% at 5-10% lower power, that s quite a remarkable achievement, now compare N7 to N5P and you ll uderstand why things were so easy for Zen 4 even with an IPC uplift that was smaller, so talking of failure is somewhat a huge stretch.
It is a failure in a broader sense: huge resource investment in the FP/AVX512 while integer was left behind, launch was delayed as they KNEW something is off with the chips/drivers/AGESA/Windows support, very poor marketing and communication from AMD's side (vague materials, no Zen 5 concrete benchmark numbers, deliberately omitting the important comparison points such as 7700X, no feedback from AMD to reviewers about the poor results they got before the NDA, etc.).If you go through AT articles about TSMC you ll notice that N4P provided only 11% better perf/Watt than N5P wich was used by Zen4, yet AMD managed to increase the perfs by 10% at 5-10% lower power, that s quite a remarkable achievement, now compare N7 to N5P and you ll uderstand why things were so easy for Zen 4 even with an IPC uplift that was smaller, so talking of failure is somewhat a huge stretch.
Zen 4 was on N5.
Dr Su reinforced that technology roadmaps are all about making the right choices and the right junctures, and explicitly stated that our 5nm technology is highly optimized for high-performance computing – it’s not necessarily the same as some other 5nm technologies out there.
It is a failure in a broader sense: huge resource investment in the FP/AVX512 while integer was left behind, launch was delayed as they KNEW something is off with the chips/drivers/AGESA/Windows support, very poor marketing and communication from AMD's side (vague materials, no Zen 5 concrete benchmark numbers, deliberately omitting the important comparison points such as 7700X, no feedback from AMD to reviewers about the poor results they got before the NDA, etc.).
The problem is that article is from January 2022 and Zen 4 was released in September 2022. The plan may have been for N5P. Ultimately, Zen 4 used N5 silicon. I remember AMD said that N5 was good enough when Zen 4 was released.I linked the article of AT where Lisa Su say that it s N5P.
AMD: We’re Using an Optimized TSMC 5nm Process
www.anandtech.com
They can't change the manufacturing node a year from launch.The problem is that article is from January 2022 and Zen 4 was released in September 2022. The plan may have been for N5P. Ultimately, Zen 4 used N5 silicon. I remember AMD said that N5 was good enough when Zen 4 was released.
The problem is that article is from January 2022 and Zen 4 was released in September 2022. The plan may have been for N5P. Ultimately, Zen 4 used N5 silicon. I remember AMD said that N5 was good enough when Zen 4 was released.
There won't be a client ddr6 platform from AMD next gen. DDR6 is squarely a server thing.If zen 6 is on ddr6 then will there be a zen 5+ on ddr5 & 3nm ?
Zen 5 was supposed to be on TSMC N3 (3nm). The plan changed. There is not a significant difference between N5 and N5P because it's based on the 5nm process that Zen 4 was designed for. There is a huge difference between 5nm and 3nm.In january 2022 they already had Zen 4 QSs on hands, otherwise they couldnt release it in September of the same year.
For a release in september mass production should be launched roughly 4 to 5 months before the first sales, it take two months from waffers entering the fab to get the packaged dies.
Another thought which someone probably already posted: what if the inter CCD latency increase was just a conscious tradeoff to save power? I doubt they will come out and just admit that, but it's possible this was a design choice to increase the power budget.
I'm guessing it's related to the new core parking which is turning off the cores on 1 CCD. This has the effect of reducing lightly threaded power consumption, see the improvements shown in TPU's testing. Theoretically it should also help gaming performance by keeping all the game threads on 1 CCD, but I think that has been a mixed bag according to reviewer numbers, but who knows if some reviewers have the driver installed correctly or not.
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Our current working theory is that this is a side-effect of AMD's core parking changes for Ryzen 9000. That cores are being aggressively put to sleep, and that as a result, it's taking an extra 100ns to wake them up. If that is correct, then our core-to-core latency test is just about the worst case scenario for that strategy, as it's sending data between cores in short bursts, rather than running a sustained workload that keeps the cores alive over the long-haul.
In january 2022 they already had Zen 4 QSs on hands, otherwise they couldnt release it in September of the same year.
For a release in september mass production should be launched roughly 4 to 5 months before the first sales, it take two months from waffers entering the fab to get the packaged dies.
Wow. Wonder how the 9900X did vs 7900X?Phoronix did a round of Ubuntu vs Windows 11 tests.
Geomean gains of 9950X vs 7950X:
* Ubuntu - 14%
* Windows 11 - 10%
What's the evidence?Zen 5 was supposed to be on TSMC N3 (3nm). The plan changed.
I'm willing to go out on a limb and suggest that Linux isn't being aggressive as Windows is on power management with the cores and clusters. That difference of 4% is similar to the suggestions that I've seen of core parking having a roughly 3% performance hit.
I still think there's something to the idea that there is a further complication in inter-CCX communications due to the new requirement to support non-symetric CCX layouts.
But then multiple people just jumped in that it is clearly a bug and Zen 5 is a dumpster fire, etc., etc. and off the the races we went with that. Now, I'm not saying we know for sure it was a design choice, but it appears that way to me. There is no increased latency from the CCDs to the memory, so it's not a reduction in latency or bandwidth in the connections themselves. Even if it is a weird bug, it appears that this has basically no effect on performance as there doesn't seem to be any actual benchmarks that are affected. Hopefully we get a good explanation of this behavior at some point from AMD, but from what I've seen, this appears to be a deliberate choice to save power, only shows up in a negative way in a purely synthetic test, and was probalby primarily designed for the mobile market (see upcoming STX Halo and Fire Range which are muli-CCD products on mobile and STX which has 2 clusters with independent L3s even though it is monolithic).
The evidence is the # of N3b (aka the real N3) designs being single digit.What's the evidence?
By the way, if you use an app that makes use (maybe extensive use) of avx-512, so far the testing done on that chip is showing over 30% improvement over the 7950x. There has already been benchmarks presented here (or in the 9700x review thread) that in a very heavy avx-512 it was getting 98% improvement. So I guess it depends on how extensively it is used. Since Zen 5 is "server first" I would not say its a dumpster fire. Its just not that much better in games or office/utility tasks. In anything scientific, its 10-98% better.lol, I never claimed it was a bug, but I did call it a dumpster fire (and I, along with many others still believe it is). Dont conflate the two!
The latencies are definitely CCX, not CCD, related, and it is 99.9% probable that it was a design choice. I disagree with you, however, that it only shows up in a negative way in a purely synthetic test. Its clearly negative to gaming. If that wasnt the case, AMD would not have required the use of the PPM provisioning driver for dual CCD/CCX Zen 5 desktop parts, which is itself a negative requirement, IMO.