Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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Jul 27, 2020
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First, the bad news:










Most of these regressions I think are due to the latency.

The real kicker is that the 7950X@5200 MT/s is beating the 9950X@5600 MT/s in some of these tests !!!

Keeping that bit of craziness in view, I think the disappointment over 9950X is justified.

Now the good news:

9950X generally does pretty well in the Pugetbench test suite.

 

jdubs03

Senior member
Oct 1, 2013
700
315
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At Computerbase the 9950X is ahead of the 14900K both in ST by 6% and MT by 10%, and at 275W for the 14900K, as for ARL it will be eventually slightly ahead only in Cinebench and that s by using 250W.

Same as the 241W 12900K wich was trounced by the 142W 5950X in almost any MT bench excepted in Cinebench, but this time ARL wont have any ST advantage, if early numbers are accurate it will be crushed in WebXPRT4, an Intel friendly browsing bench, and Speedometer and sligthly below in GB, wich is telling about its SC perf.
ARL is supposed to consume much less power. I think you’re underestimating this.
And it’ll likely be a good bit better in gaming.
 
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sl0519

Junior Member
Aug 10, 2024
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ARL is supposed to consume much less power. I think you’re underestimating this.
And it’ll likely be a good bit better in gaming.

We don't know how much the IPC uplift will come into play. Zen 5 did get those uplifts, but it's not showing in games, whereas Zen 3 got a pretty massive boost in games with its claimed IPC uplift.
 

Josh128

Senior member
Oct 14, 2022
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Hans Gruber

Platinum Member
Dec 23, 2006
2,297
1,212
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I wish you would start using the modern node names. RPL is on "Intel 7". Rumor is last I checked ARL will use 3N for higer end and Intel 20A for lower end chips. There is no "intel 5" and 20A is not "5nm".

Zne 5+ has been a popular idea since Zen 5 came out pretty crappy. The early ARL numbers aren't looking great though at least for ST. In MT Skymont seems to do well. I expect the 9800X3D will be the most popular when it comes out assuming AMD doesn't delay those too.
I think you have it backwards. The high end Intel chips will be made with 20A silicon. I think the low end Intel offerings are any CPU's below what we know as i3 CPU's. Those could be made with TSMC silicon.

Based on how silicon has been measured historically. Intel 20A silicon is essentially 5nm. I didn't say it. That is what has been published all over the web for several years. Intel has said for many years that their silicon offers much more density than TSMC silicon. Intel is halving their process node from 10nm to 5nm. That is a huge jump in size compared to TSMC going from 7nm to 5nm to 3nm.

There is no comparing the 14th generation to Arrow Lake 20A. The performance uplift and power efficiency gains may put it ahead of what N4P has done for Zen 5. That is what a lot of people have ignored. Many assume that Arrow Lake is Raptor Lake's next act. The reality is totally new silicon with a different architecture scheme.

People who do not take sides in the AMD vs Intel battle have been waiting for Arrow Lake because of the new silicon node. Like me, they want to see what it can do. The upcoming Arrow Lake CPU's are said to be from 65w TDP to 150w TDP for the highest end CPU's. I have heard the non K series CPU's will be 65w up to at least Intel 7 series.

I said before Zen 5 was released that a Zen 5+ with N3P would be necessary because of 20A and 18A further down the road from Intel.
 

Hitman928

Diamond Member
Apr 15, 2012
6,058
10,397
136
First, the bad news:

View attachment 105567

View attachment 105568
View attachment 105569
View attachment 105570
View attachment 105571
View attachment 105572
View attachment 105573

Most of these regressions I think are due to the latency.

The real kicker is that the 7950X@5200 MT/s is beating the 9950X@5600 MT/s in some of these tests !!!

Keeping that bit of craziness in view, I think the disappointment over 9950X is justified.

Now the good news:

9950X generally does pretty well in the Pugetbench test suite.


First, Pudget results should always be taken with some salt, IMO, because they make very manual, and sometimes weird, setup choices on their systems. Second, multiple of those are well within margin of error which indicates some other bottleneck, but beyond that, if it was because of the added core to core latency, why are others showing better results in Photoshop and Premier? Also, if you take the full DaVinci Resolve AI chart, the results are all over the place (e.g., the 9700x is way faster than the 7700x but the 9600x and 7600x are basically tied; the 9900x and 7900x are faster than everything except the 9700x so where is the cross CCD penalty?).











Even if you ignore the tests from other outlets and just look at the whole graphs that you clipped, there's no consistency in there being a cross CCD penalty when you look at the other CPUs involved as well (i.e., 9900x and Zen 4 CPUs).
 

Hitman928

Diamond Member
Apr 15, 2012
6,058
10,397
136
I think you have it backwards. The high end Intel chips will be made with 20A silicon. I think the low end Intel offerings are any CPU's below what we know as i3 CPU's. Those could be made with TSMC silicon.

This should be taken to the Intel thread, but all of the "leaks" have said that all of the high end SKUs and the majority of SKUs for ARL will be on TSMC 3B. The 20A SKUs will be mid-range and low volume. Maybe they are all wrong, but that has been the consistent leak thus far.
 

coercitiv

Diamond Member
Jan 24, 2014
6,599
13,953
136
Anyone tried it on Intel yet?
Not even people payed to do it are interested in doing it, and even if they did, the goalpost for Zen 5 gaming performance would shift somewhere else.

For instance, there is increasing evidence that Zen 5 performs up to 10% better in games when testing during a full moon. We hope reviewers will test this claim thoroughly in the next few days, otherwise we'll have to wait for another month to get proper testing conditions. If true, this find could have astronomical implications.
 
Last edited:

Hans Gruber

Platinum Member
Dec 23, 2006
2,297
1,212
136
This should be taken to the Intel thread, but all of the "leaks" have said that all of the high end SKUs and the majority of SKUs for ARL will be on TSMC 3B. The 20A SKUs will be mid-range and low volume. Maybe they are all wrong, but that has been the consistent leak thus far.
The compute unit/tile is what they are talking about. Fabricated on N3 3nm silicon. That is only part of the CPU. The rest of the CPU will be on Intel 20A silicon.
 

Steltek

Diamond Member
Mar 29, 2001
3,200
977
136
Not even people payed to do it are interested in doing it, and even if they did, the goalpost for Zen 5 gaming performance would shift somewhere else.

For instance, there is increasing evidence that Zen 5 performs up to 10% better in games when testing during a full moon. We hope reviewers will test this claim thoroughly in the next few days, otherwise we'll to wait for another month to get proper testing conditions. If true, this find could have astronomical implications.
I thought that only applied if you did the testing while dancing under the moonlight of the full moon wearing only a tinfoil hat?
 

yottabit

Golden Member
Jun 5, 2008
1,483
514
146
First, the bad news:

View attachment 105567

View attachment 105568
View attachment 105569
View attachment 105570
View attachment 105571
View attachment 105572
View attachment 105573

Most of these regressions I think are due to the latency.

The real kicker is that the 7950X@5200 MT/s is beating the 9950X@5600 MT/s in some of these tests !!!

Keeping that bit of craziness in view, I think the disappointment over 9950X is justified.

Now the good news:

9950X generally does pretty well in the Pugetbench test suite.

That's interesting. I know for at least Unreal Engine - Compile shaders, it's a very memory bandwidth sensitive task. Guessing same may go for many of these

They did some prior memory channel scaling tests here https://www.pugetsystems.com/labs/articles/amd-threadripper-pro-memory-channel-performance-scaling/

Looks like Premiere and After Effects are also sensitive but not as much

But don't worry, I'm sure all the "AMD should release a 32 core desktop CPU with 2 channel memory people" don't care

 

JustViewing

Senior member
Aug 17, 2022
216
382
106
But don't worry, I'm sure all the "AMD should release a 32 core desktop CPU with 2 channel memory people" don't care
Do you realize the above is using DDR4? Regardless it is not whether there will be memory bottleneck or not, it is more like 24/32 core Zen4/5 processor will beat 16 core Zen4/5 processor in multi threaded tasks. It is a better approach than trying to go 6Ghz 16 core CPU. There is no reason for AMD to concede multi threaded performance to Intel.
 
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IEC

Elite Member
Super Moderator
Jun 10, 2004
14,437
5,417
136
Let's see:
Impressive efficiency (meh)
Bugs (yes)
So-so speed boosts (yes)
High prices (relative to performance)
Already-expensive AM5 platform (sure, compared to AM4)

Overall I give them 3.5/5 "Meh"s for effort on that review. And 11/10 "Meh"s to AMD for their consumer-facing Zen5 products.
 

DrMrLordX

Lifer
Apr 27, 2000
22,003
11,569
136
I wrote clearly that you should support your claim as best you can.

MLID didn't support his claim at all, so why is anyone defending it?

To AMD employees who are also reading this thread.
I have seen various tests of the 9950x. After 2 years of work on ZEN 5, hundreds of changes and architecture improvements, it is obvious that in a hurry the engineers made a mistake somewhere and SOMETHING is seriously blocking the performance of this CPU. There is a bottleneck somewhere/something that effectively negates the potential of all these improvements in ZEN 5.
That or AMD is appealing directly to their largest/most lucrative markets instead of attempting to appeal to everyone with their latest design. Months ago I was flabbergasted when @adroc_thurston suggested that Zen5 would be the last gen to share CCDs with server/workstation, but maybe now it makes more sense.
 

dr1337

Senior member
May 25, 2020
414
680
136
But don't worry, I'm sure all the "AMD should release a 32 core desktop CPU with 2 channel memory people" don't care

View attachment 105584
If we're considering DDR4 bandwidths here, and the 24c chip is still faster than the bandwidth constrained 64c, why would a 32c on dual channel DDR5 be so much worse? If anything it would be a lot faster with these newer architectures being (relatively) more bandwidth efficient. Or, at least, they'd be able to field 24c/48t on standard DDR5 just fine.


Everything has its gives and takes, Zen 5 doesn't do much for gaming yet phoronix finds it to be the fastest on the block for literally everything else.

A lot of people are calling it a flop because in select workloads its a marginal improvement, yet in others it makes a great deal of improvement. This same idea applies to every aspect of CPU design including absolute core counts. Some workloads need memory bandwidth and other will prefer more logic units in total. Its just the way she goes.
 

yottabit

Golden Member
Jun 5, 2008
1,483
514
146
If we're considering DDR4 bandwidths here, and the 24c chip is still faster than the bandwidth constrained 64c, why would a 32c on dual channel DDR5 be so much worse? If anything it would be a lot faster with these newer architectures being (relatively) more bandwidth efficient. Or, at least, they'd be able to field 24c/48t on standard DDR5 just fine.


Everything has its gives and takes, Zen 5 doesn't do much for gaming yet phoronix finds it to be the fastest on the block for literally everything else.
View attachment 105602
A lot of people are calling it a flop because in select workloads its a marginal improvement, yet in others it makes a great deal of improvement. This same idea applies to every aspect of CPU design including absolute core counts. Some workloads need memory bandwidth and other will prefer more logic units in total. Its just the way she goes.
The people saying “more coars because DDR5 is faster” are neglecting to remember that the new cores are more powerful, have more throughput, and thus require more bandwidth per-core. That seems pretty common sense?

Maybe you could support a hypothetical 24 or 32 Zen3 cores on dual channel EXPO DDR5 and have good performance for most workloads. Maybe even a 24 core Zen4. But clearly Zen5, especially when running in AVX 512 is a memory bandwidth hog.

There are surely plenty of workloads that aren’t membw sensitive, but there are also plenty that are (and some that you may not intuitively think such as shader or code compilation) I think this is one area Intel’s hybrid approach has an advantage.

For membw bound workloads you get the 8 fastest cores available to get a great ratio of throughput-per-p core, and for tasks that aren’t membw bound you can use the e-core spam.

I think Zen5 highlights more than any previous generation the insufficiency of memory bandwidth for these 16 cores. It’s bottlenecking harder than ever in some workloads. Why would you want to keep pushing those diminishing returns? It’s also needing full socket power with PBO to maximize MT perf, and there’s still you guys that want more cores? Lol
 
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Thibsie

Senior member
Apr 25, 2017
856
964
136
AMD has failed before with products - e.g. Vega, RDNA3, Bulldozer. They weren't a failing of marketing, but a failing of engineering. Marketing could have saved at least RDNA3, but no amount of time would've fixed them. Ryzen 9000 isn't this huge failure like them, although from those mentioned it is most similar to RDNA3. It's just a disappointment.
Oh yeah Bulldozer was a marketing failure. Calling their modules dual core was a failure and it cost them. And rightly so.
 
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Fjodor2001

Diamond Member
Feb 6, 2010
3,989
440
126
The people saying “more coars because DDR5 is faster” are neglecting to remember that the new cores are more powerful, have more throughput, and thus require more bandwidth per-core. That seems pretty common sense?
DDR5 is roughly twice as fast as DDR4. Are the new cores on DDR5 twice as fast as the latest cores on DDR4? Do they require twice the memory bandwidth?
But clearly Zen5, especially when running in AVX 512 is a memory bandwidth hog.
Depends on what kind of workload and data you're using AVX512 for. If the amount data being processed is limited, it'll be kept in cache which fast and has very high memory bandwidth. Same as for other operations BTW. Not sure why AVX512 should be special in this regard.

Also, not all MT workloads use pure AVX512 anyway. Instead it's probably very few actually.
I think Zen5 highlights more than any previous generation the insufficiency of memory bandwidth for these 16 cores.
Source for this claim?
Why would you want to keep pushing those diminishing returns?
Because for ideal MT workloads, you can double performance by doubling number of cores. This is technically quite easily achievable by adding more CCX dies. So it's a relatively easy way to improve MT performance a lot. And even if the MT workloads are not ideal, you'll still get a massive MT performance increase by increasing number of cores.

If you want to archive the same MT performance improvement while using same number of cores, you'll have to double ST performance. Which we've seen is not easily doable. Not even close. We're now in the 5-10% improvement per 1-2 years territory for Zen.
 
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