Are you sure about that?other chips may be limited by thermals due to higher power/mm2.
Are you sure about that?
What he is referring to is common knowledge. Zen5, if what we know so far, is moving to a wider front end, soft of like Apple's SoCs. This will boost IPC, but also limit the Zen5 designers who want to keep power in check and not create excessive hot spots. Obviously, AMD is going for a net gain in performance. All those new xtors will draw more power and AMD will need to keep clocks (really voltage) down to hit the Power per Watt metrics that they set for themselves. There isn't a big process change here, so there will be no 'free' power savings that could be translated into faster clocks. It's always tradeoffs between architecture, implementation and process limitations - that why large IPC jumps aren't free. This isn't the best explanation, but i hope it helps.So this means its just your own conjecture, but there is otherwise no source to support that?
It's a pretty chonky core, so heat density will be a-ok.I m talking of Zen 5.
The numbers are just bogus but I digress.That being said it s possible that the lower cores parts are frequency limited on purpose.
Yeah, based on what I've read in this thread, along with other posts on Twitter, it looks like Zen 5 is shaping up to be a ST beast by sporting a >30% IPC boost and massively improved front end, but it is held back in MT due to IF bandwidth limitations via re-use of the IOD from Zen 4. Allegedly, Zen 6 ameliorates the MT issue with what I presume is a new IOD, but still on the AM5 socket. Given that there's little to no process gain for desktop Zen 5 (N5 to N4P), the perf/W and max clock increase has been hinted at being relatively non-existent over DT Zen 4. Lastly, Zen 5 is supposed to support wider AVX and more AI instructions.What he is referring to is common knowledge. Zen5, if what we know so far, is moving to a wider front end, soft of like Apple's SoCs. This will boost IPC, but also limit the Zen5 designers who want to keep power in check and not create excessive hot spots. Obviously, AMD is going for a net gain in performance. All those new xtors will draw more power and AMD will need to keep clocks (really voltage) down to hit the Power per Watt metrics that they set for themselves. There isn't a big process change here, so there will be no 'free' power savings that could be translated into faster clocks. It's always tradeoffs between architecture, implementation and process limitations - that why large IPC jumps aren't free. This isn't the best explanation, but i hope it helps.
Sorta but power isn't free either way.but it is held back in MT due to IF bandwidth limitations via re-use of the IOD from Zen 4
Atta.Allegedly, Zen 6 ameliorates the MT issue with what I presume is a new IOD
You must be alluding to that whole discussion about a future Zen core being there for ST purposes only (e.g. no SMT) and having Zen 5c or Zen 6c cores to provide the MT performance.Atta.
It's a very very different approach to system design.
Plus it's on N3p which means more nT perf as is.
No.You must be alluding to that whole discussion about a future Zen core being there for ST purposes only (e.g. no SMT) and having Zen 5c or Zen 6c cores to provide the MT performance.
Did you actually read my post? Because I clearly listed Arrow Lake, Zen 5 and Luna Lake.Should we take your previsions for ARL 8 + 16 in the post you linked as an exemple of your accuracy for Zen 5 as well.?.
Because ARL numbers recently leaked say that you are off by 2.4X for TDP and "only" by a 200% factor for perfs improvements.
Historically speaking this isn't true at all for AMD. There has been non-stop clock increases with every Zen iteration. Not saying it isn't logical or isn't possible that Zen 5 breaks the cycle, but some random conjecture isn't much compared to history.It's always tradeoffs between architecture, implementation and process limitations - that why large IPC jumps aren't free.
Or you're making things up just because its fun to you. You made it a point to specifically diss other 'leakers' yesterday so surely you understand why people are skeptical of your very confidently made statements. Other leakers that you probably wouldn't label as "idiots" won't speak with so much ego unless their name is Charlie Demerjian. Maybe you really are under NDA but all I sense is LARP.I mean, yea.
One never rats people out just because.
I don't want to summon my usual crew to verify anything (but they lurk here too).Or you're making things up just because its fun to you
youtube e-beggars aren't leakers.You made it a point to specifically diss other 'leakers' yesterday so surely you understand why people are skeptical of your very confidently made statements
Are you part of the team of Neanderthals that Userbenchmark accuses of leading a gorilla campaign all over the internet to promote AMD products?I don't want to summon my usual crew to verify anything (but they lurk here too).
Hey, aint nothin wrong with gorillas! 🦍Are you part of the team of Neanderthals that Userbenchmark accuses of leading a gorilla campaign all over the internet to promote AMD products?
So what, 6 years of AMD history is sufficient for you, as opposed to the past 30 years of CPU history. Or 20. Or 10 (when AMD was in the dumpster). Come on man, your view is just too short sighted.Historically speaking this isn't true at all for AMD. There has been non-stop clock increases with every Zen iteration. Not saying it isn't logical or isn't possible that Zen 5 breaks the cycle, but some random conjecture isn't much compared to history.
I hope so, always wanted to be a manifestation of someone's schizophrenia.Are you part of the team of Neanderthals that Userbenchmark accuses of leading a gorilla campaign all over the internet to promote AMD products?
Yea clock juice ran out.So what, 6 years of AMD history is sufficient for you, as opposed to the past 30 years of CPU history. Or 20. Or 10 (when AMD was in the dumpster). Come on man, your view is just too short sighted.
that's him? in his videos he looks like a dodgy fat boy with a persistent hygeine problem who should be kept 300 meters away from primary schools.
Is it really? Isnt intel also pushing 12th, 13th and 14th gen to higher clocks than ever before? And doesn't alder lake technically have a wider architecture? AMD lost clocks with Zen 1 compared to bulldozer but its just a fact that an architecture can clock better or worse than another. Hence why its even arguable at all.Come on man, your view is just too short sighted.
With shrinks, yes.Haven't clocks also just gone up in general?
It's a very wide core, high clock isn't the target there.You're calling me short sighted but it would only appear you two are ignorant here.
20% IPC is what Zen3 benched, and that was a tiny machine that got its key feature pulled into Zen2.but historically there is nothing physically preventing a 20% ipc boost and 100-200mhz more clocks with a revised arch and a mild node jump.
That's debatable. Fairy certain proper backside power delivery will create frequency gains.N5 was the last major one for speed until like the CFET era.
Tiny.Fairy certain proper backside power delivery will create frequency gains.
Did you actually read my post? Because I clearly listed Arrow Lake, Zen 5 and Luna Lake.
Also are you sure about your numbers? I assume you refer here to Igor's Lab's leaks.
Intel’s internal performance projection for Raptor Lake S Refresh and Arrow Lake S - How fast the CPU and iGP are expected to be | Exclusive | igor´sLAB
The Raptor Lake refresh is expected to arrive this year as the 14th CPU generation for the desktop. But the real successor, Arrow Lake-S for desktop, is also increasingly materializing along with the…www.igorslab.de
First you are not citing TDP but PL1 and PL2. If you look at the listing for example for Raptor Lake seen here:
You will notice that for RPL TDP 125W it got PL1=188W; PL2=238WIntel 13th Gen Raptor Lake-S PL1, PL2, PL4 Power Values Surface: Fine Tuning and Slight Increase | Hardware Times
German outlet Igor’s Lab has posted the power values of Intel’s 13th Gen Raptor Lake-S processors and how they vary compared to the preceding lineup (Alder Lake). A brief look at the figures indicates that the load power consumption (PL2) has gone slightly up, with the absolute max draw (Iccmax)...www.hardwaretimes.com
As for the 200% number it's referred to the iGPU not the CPU. Other articles referring to Igor's even say that like this one:
Yeah we knew that already, it's just a question of double the 256bit pipes or double width of existing pipes
Have you heard of any plans to design FIVR-based PDN for Zen6?It's a very very different approach to system design
They already have built in regulators per core since Zen 1, what Intel will implement as DLVR.Have you heard of any plans to design FIVR-based PDN for Zen6?