This may not work as Zen5 likely to have additional instructions added to it. AMD don't want to end up like Intel and have to disable these new instruction for the sake of supporting Zen4c.AMD can just save costs by using 8P chip + 16E chip in the form of Zen5 + Zen4c. The down bins from Turin and Bergamo sold to consumers to save money. TSMC is no longer offering discounts to even their largest customers.
I'm not personally convinced it'll happen, but if the differences are small enough, they can probably get away with it. Minor things like RAS shouldn't matter for mainstream desktop.This may not work as Zen5 likely to have additional instructions added to it. AMD don't want to end up like Intel and have to disable these new instruction for the sake of supporting Zen4c.
While Intel uses entirely different architectures, ZenX and ZenXc are basically the same. At least for Zen4 AMD promised full ISA compatibility. And while the first speculation was that they would combine Zen5 and Zen4c, to me it seems much more likely now that they would combine the same generation after all the bad coverage Intel got.This may not work as Zen5 likely to have additional instructions added to it. AMD don't want to end up like Intel and have to disable these new instruction for the sake of supporting Zen4c.
While Intel uses entirely different architectures, ZenX and ZenXc are basically the same. At least for Zen4 AMD promised full ISA compatibility. And while the first speculation was that they would combine Zen5 and Zen4c, to me it seems much more likely now that they would combine the same generation after all the bad coverage Intel got.
I really doubt either AMD or Intel care about some of the internet whining about hybrid, especially when half of it seems to only be because it's Intel doing it. The actual results speak for themselves.While Intel uses entirely different architectures, ZenX and ZenXc are basically the same. At least for Zen4 AMD promised full ISA compatibility. And while the first speculation was that they would combine Zen5 and Zen4c, to me it seems much more likely now that they would combine the same generation after all the bad coverage Intel got.
I really, really doubt that's the direction AMD goes. Not going to say it's outright impossible, but it seems like a massive overhead. Would be a nightmare from the OS's perspective. That "rumor" reads more like uninformed speculation.The rumour from months (years?) ago (but IMO more relevant for laptop market) was that they'd combine a small core and a big core with different ISA BUT...
the different ISA was pretty much intended, an illegal instruction on the small core would wake the big core
I really, really doubt that's the direction AMD goes. Not going to say it's outright impossible, but it seems like a massive overhead. Would be a nightmare from the OS's perspective. That "rumor" reads more like uninformed speculation.
I mean, sure, if you're willing to literally burn an entire extra CPU core, maybe you can simplify things somewhat. But that's a frankly absurd tradeoff for anyone to suggest, much less for merely ISA compatibility.Agreed except for the OS point. The thing is the OS is not NOT seeing two cores. The OS is NOT aware of all this. This was supposed to be dealt with IN the CPU intself.
How realistic, dunno. But would eliminate the OS as a variable.
That's not a rumor but an actual patent AMD filed quite some time ago (edit: filled on 10/27/2017, published on 06/30/2020)The rumour from months (years?) ago (but IMO more relevant for laptop market) was that they'd combine a small core and a big core with different ISA BUT...
the different ISA was pretty much intended, an illegal instruction on the small core would wake the big core and the thread would continue execution seamlessly on the big core (but maybe back to the small one depending situation). Seems this also imlied shared register (yeah, I know).
This meant that one can't say thee're two cores. Not really. This rather is a hybrid of two cores but only one is ever active at a time.
That was the rumour circulating at the time.
How much of this was really intended as a real product, who knows ?
Zen+ has actually 5% better IPC than Zen.
If we exclude games and using Zen 1 as basis the evolution is 21%, 34% and 51% respectively for Zen 2/3/4, Zen 4 brought a slightly better IPC improvement than Zen 3 vs Zen 2.
Btw Zen 4 has 2% better MT IPC than ADL/RPL on a 8C comparison basis.
AMD Ryzen 7000 im Test: So schnell sind 7950X und 7700X
AMD Ryzen 7000 ist da. Im ausführlichen Test treten Ryzen 9 7950X und Ryzen 7 7700X mit Zen-4-Kernen gegen Ryzen 5000 und Intel Core an.www.computerbase.de
Zen+ was always an interesting release. AMD claimed IPC improvements, but these were improvements Threadripper 1xxx already had. Where did they come from? The clocks came from slightly improved process.
Was about to say the same thing.This may not work as Zen5 likely to have additional instructions added to it. AMD don't want to end up like Intel and have to disable these new instruction for the sake of supporting Zen4c.
In German we call software and hardware that is supposed to fix itself in the hands of consumers bananaware. Ryzen 1000 was such an unripe banana.
AMD "releases" a new APU gen each CES. CES 2023 is Zen 4-based Phoenix. We don't have info about any "Zen 4+"-based APU. Thus the 2024 APU should be the Strix Point.Based on Angstronomics' claim that Strix Point will be announced in January 2024/CES and MLID's claim that Turin is H1 2024 (which I only take seriously because it lines up with the former), what are the odds of a Q1-Q2 2024 Granite Ridge/Ryzen 8000 launch? AMD does seem to be pushing more and more stuff in shorter timeframes. Although I'll admit the Ryzen 5000 near-2 year old freeze is the outlier, not the new normal for AMD, we'll probably be going back to the Zen-Zen3 cadence or faster. Especially if Intel manages to finally pull another Tiger Lake/"10nm SF" with Meteor Lake/"Intel 4" (still doubtful for now tho).
Does just changing cache sizes count among cores on the same package as "big.LITTLE" core setups? Pertinent question IMO. Pretty sure AMD isn't interested in "LITTLE" cores in the ARM/Intel sense anyway.Here is old rumor but a news to here that Zen5 is not big-little. IIRC he is Greymon on twitter. He got info from AMD package facility.
View attachment 70171
I have a wild speculation that 2 CCDs have been unified as one on die package level.
I would say so. You still have different performance/area levels and have to deal with all the software scheduling that goes with such designs.Does just changing cache sizes count among cores on the same package as "big.LITTLE" core setups?
I don't think Intel and ARM are doing little cores in the same way. ARM is for improving efficiency, esp when big cores aren't needed, but Intel is using little cores to improve performance, afaik. Which is why the number of little cores for processors such as Apple chips aren't really increasing, but Intel doubled e-cores for raptor lake. I think AMD is going to use little cores more akin to the Intel method.Pretty sure AMD isn't interested in "LITTLE" cores in the ARM/Intel sense anyway.
I think AMD's definitely trending more towards and Intel-like solution than an Apple one. Not saying they will, but if AMD actually does use a last-gen/cut-down core paired with the current, full fat one, then that would probably be a similar performance gap compared to Atom vs Core.Pretty sure AMD isn't interested in "LITTLE" cores in the ARM/Intel sense anyway.
I would say so. You still have different performance/area levels and have to deal with all the software scheduling that goes with such designs.
I don't think Intel and ARM are doing little cores in the same way. ARM is for improving efficiency, esp when big cores aren't needed, but Intel is using little cores to improve performance, afaik. Which is why the number of little cores for processors such as Apple chips aren't really increasing, but Intel doubled e-cores for raptor lake. I think AMD is going to use little cores more akin to the Intel method.
Here is old rumor but a news to here that Zen5 8000 series is not big-little. IIRC he is Greymon on twitter. He got info from AMD package facility.
View attachment 70171
I have a wild speculation that 2 CCDs have been unified as one on die package level.
And AMD's mobile cores so far have been about saving power, saving area and higher density, but not changing ISA features.Apple & ARM little cores are primarily about saving power. Intel's little cores are primarily about saving area.
Which people can't buy en masse till July or August....AMD "releases" a new APU gen each CES. CES 2023 is Zen 4-based Phoenix.