Which is exactly why I chose it and AMD just read my post and named it so.A codename is ultimately chosen because someone sufficiently high up thinks it sounds cool
Morpheus is also part of Greek mythology.That being said the codenames for Zen3 (Cerberus) and Zen4 (Persephone) are at least closely related underworld stuff in Greek mythology.
I don't see how Nirvana and Morpheus are related at all 🤔, definitely does sound like someone was just watching Matrix Resurrections when they started work on it.
IIRC, Zen 6 might be going back to the team that did Zen 3/4. If that's the case, would explain the change in naming.Morpheus is also part of Greek mythology.
AMD likes to switch back and forth with codename schemes for some reason. Just look at Summit Ridge/Pinnacle Ridge -> Matisse/Vermeer/Raphael (painters) -> back to Granite Ridge. And Zen6 desktop uses a codename related to the Greek underworld mythology also
YesIIRC, Zen 6 might be going back to the team that did Zen 3/4. If that's the case, would explain the change in naming.
Hydra?Morpheus is also part of Greek mythology.
AMD likes to switch back and forth with codename schemes for some reason. Just look at Summit Ridge/Pinnacle Ridge -> Matisse/Vermeer/Raphael (painters) -> back to Granite Ridge. And Zen6 desktop uses a codename related to the Greek underworld mythology also
Hades more like if I would guess.Hydra?
MorpheusCore Architecture and Product teams are managed differently and by different people.
Mike Clark's Team (Core Roadmap)
Valhalla--> Cerebrus --> Persephone --> Nirvana --> Morpheus . The code names for the core arch seems to be not exclusively Greek Mythology based.
Product/SoC Teams:
Client Compute
Summit/Pinnacle Ridge --> Matisse --> Vermeer --> Raphael --> Granite Ridge
Raven Ridge --> Renoir --> Phoenix Point --> Strix Point
Server Compute
Naples --> Rome --> Milan --> Genoa
5 years ago it seems much of the work is done by the same folks but now they do have specialized teams doing different things, Core, Fabric, Exascale, Process, Packaging, etc.
But it could be possible someone sold me a fairy tale.
Hades more like if I would guess.
Update:
Seems Process and Foundry Tech Leader and pioneer Rich Schulz retired from AMD this month, wondering if it is "retirement" or something else.
That's just a regurgitation of Nosta's screenshot of that AMD employee's LinkedIn profile that had the core codenames and node processes that everyone else on Twitter found and wrote articles about. We've come full circle.
Yes, what's old is new and what's new is old. Having processors be multi-node is just a modern form of tick-tock, except the ticks include optimization nodes instead of full nodes.Zen 6 would be multi node anyway just like Zen 5 is. There will likely be a Zen 6 on N3E or N3P. Forrest Norrod already stated going forward you can expect diversity of nodes for every upcoming generation.
Ok, I haven't been following this thread closelyThat's just a regurgitation of Nosta's screenshot of that AMD employee's LinkedIn profile that had the core codenames and node processes that everyone else on Twitter found and wrote articles about. We've come full circle.
Lol, no worries. I just find it funny how rumors come back to their origin.Ok, I haven't been following this thread closely
Yep, people here seem quick to forget that Zen and Zen+, in most ways the same core designs, where on 2 different nodes. Or even worse, most recently, Zen3 and Zen3+/Cezanne and Rembrandt are also a similar story. So AMD is no stranger to this.Zen 6 would be multi node anyway just like Zen 5 is. There will likely be a Zen 6 on N3E or N3P. Forrest Norrod already stated going forward you can expect diversity of nodes for every upcoming generation.
Because both 4 and 3nm variants of Zen 5 are supposed to come out in 2024, and it doesn't make much sense to me IMO to release Zen 5 and Zen 5+ in the same year when AMD is already on a 1.5 year pace, and Zen 5 should be comfortable in terms of performance with it's competitors as well.Yep, people here seem quick to forget that Zen and Zen+, in most ways the same core designs, where on 2 different nodes. Or even worse, most recently, Zen3 and Zen3+/Cezanne and Rembrandt are also a similar story. So AMD is no stranger to this.
Even tho they'll likely make bigger inter-generational node jumps (bigger urach changes as well or just more power/perf?) now going forward. I'm already thinking of Zen5 and Zen5+ and Zen6 and Zen6+ will be things. Strange that from what I've read and watched, no one seems to even conceive that we might be getting a "Zen5+" as well. It's all just about "is Zen5 on '4nm' or '3nm'? hmmm"
I wasn't talking about the core name, but the codename of the Zen6 desktop product itself.That's just a regurgitation of Nosta's screenshot of that AMD employee's LinkedIn profile that had the core codenames and node processes that everyone else on Twitter found and wrote articles about. We've come full circle.
Exactly - it's a necessity to combat node share problems in the case of other players buying up capacity.Zen 6 would be multi node anyway just like Zen 5 is. There will likely be a Zen 6 on N3E or N3P. Forrest Norrod already stated going forward you can expect diversity of nodes for every upcoming generation.
14nm/12nm and N7/N6 are both design compatible, so AMD had to do little to no work to support both. If we truly see full fat Zen 5 on both N4 and N3, that would be a notable departure.Yep, people here seem quick to forget that Zen and Zen+, in most ways the same core designs, where on 2 different nodes. Or even worse, most recently, Zen3 and Zen3+/Cezanne and Rembrandt are also a similar story. So AMD is no stranger to this.
N3 is more of a minor node jump from N5 compared to even N7 -> N5, let alone N16 -> N7.Even tho they'll likely make bigger inter-generational node jumps (bigger urach changes as well or just more power/perf?) now going forward
Leaving out density for a moment, N5 --> N3E is on par in terms of perf and efficiency vs N7 --> N5 as per TSMC data.N3 is more of a minor node jump from N5 compared to even N7 -> N5, let alone N16 -> N7.
TSMC are basically wringing one last full node out of finFET before they switch to GAA / Nanosheet / MBCFET for N2, which will require a significant pitch shrinkage to achieve the same density owing to the reduced area efficiency of Nanosheet relative to finFET.
Forksheet FET evolves that transistor design further exceeding the area efficiency of finFET, but that will be a few more years down the line from N2, 2028 maybe.
SRAM doesn't scale at all N5->N3E. https://fuse.wikichip.org/news/7343/iedm-2022-did-we-just-witness-the-death-of-sram/Bulk of Analog+IO is already off die anyway, and SRAM is main issue with 1.2x scaling with N5 --> N3E compared to 1.35x scaling on N7 --> N5
What’s interesting is, for the new N3E node, the high-density SRAM bitcell size as not shrunk at all. Coming in at 0.021 µm², this is exactly the same bitcell size as their N5 node.