Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[adroc_thurston]

My theory is that Zen benefits greatly from the schedule and execution ports, separate for the FPU and separate for the ALU.

You're trying to boil down CPU performance factors to a single metric.
That's really-really not how it works!

 

[rainy]

You're trying to boil down CPU performance factors to a single metric.
That's really-really not how it works!

You must understand, that despite of his nickname, he's devoted Intel user with a rather strange fetish for numbers.

Fan, fanboy, stan, etc. are allowed in the tech forums as they are used derogatorily far more often than not.

Thanks for your understanding and cooperation

Mod DAPUNISHER

 

[adroc_thurston]

You must understand, that despite of his nickname, he's devoted Intel fan with a rather strange fetish for numbers.

Yeah but he's trying to model CPU perf in the most in(s)ane way possible.

 

[AMDK11]

You're trying to boil down CPU performance factors to a single metric.
That's really-really not how it works!

This is one of many factors and I am not saying it is the most important one.

This is the only way to find out and compare with Zen because LionCove separates the FPU ports from the ALU ports.

 

[adroc_thurston]

This is one of many factors and I am not saying it is the most important one.

It's not really one relevant to Zen5 at all.
You can just find the C&C article where Clam profiled 7950X in vidya to see the key back-end issues.

This is the only way to find out and compare with Zen because LionCove separates the FPU ports from the ALU ports.

You. Just don't.

 

[AMDK11]

It's not really one relevant to Zen5 at all.
You can just find the C&C article where Clam profiled 7950X in vidya to see the key back-end issues.
View attachment 98662

You. Just don't.

These are just two examples of online gaming among many applications and loads.

 

[adroc_thurston]

These are just two examples of online gaming among many applications and loads.

Most client workloads are like gaming: horribly front-end bound, and when they're not, throw ROB slots at it.
Like, this is why MTL is an IPC regression in client w/l's. Same core, same boundaries, worse memory setup!

Smarter people already did the profiling for you. All you gotta do is read the charts. Not that hard.

 

[AMDK11]

Most client workloads are like gaming: horribly front-end bound, and when they're not, throw ROB slots at it.
Like, this is why MTL is an IPC regression in client w/l's. Same core, same boundaries, worse memory setup!

Smarter people already did the profiling for you. All you gotta do is read the charts. Not that hard.

So you're saying that AMD added 2 ALUs to Zen 5 for no reason, because 4 ALUs in Zen4 is not a limitation?

 

[adroc_thurston]

So you're saying that AMD added 2 ALUs to Zen 5 for no reason

well there gotta be some.

because 4 ALUs in Zen4 is not a limitation?

Not the main one, no.
Consult the chart.

 

[AMDK11]

well there gotta be some.

Not the main one, no.
Consult the chart.

AMD must consider the entire spectrum of workloads, not just games. Zen5 is designed not only for consumer computers, but also for Epyc.

Are there examples of profiling for other workloads/applications?

 

[adroc_thurston]

AMD must consider the entire spectrum of workloads, not just games

Thank you for stating the obvious and not reading what I've said before.

Zen5 is designed not only for consumer computers, but also for Epyc.

It's designed for client and cloud (and so is Zen6), these kinda share workload footprints, a lot being membound JITs and all.

Are there examples of profiling for other workloads/applications?

Pay me and I'll do it.

 

[Jayzen]

I still see very little reason to believe a 30-40% IPC uplift from either side (let alone more) is at all realistic in 2024.
To clear the air about my supposed partisan allegiance: I think Arrow Lake's going to be quite disappointing as well, and already called out Royal Core as essentially being Bulldozer with more money thrown at it.

 

[Joe NYC]

Just for context , Zen 4 was ~10-12% uplift with some minor tweaks versus Zen 3. If Zen 5 ends up being just 10-15% faster at iso clocks versus Zen 4*, then something went wrong in the design process. AMD has such advanced internal performance modeling tools that I find it impossible they would waste so much time and money to get so little out of it.

Don't forget the leak from High Yield guy:

https://twitter.com/x/status/1779094167072702813

 

[adroc_thurston]

I still see very little reason to believe a 30-40% IPC uplift from either side (let alone more) is at all realistic in 2024.

why.

I think Arrow Lake's going to be quite disappointing as well

ARLs are worthless memeparts.
Only LNL exists.

 

[Mopetar]

Well, a 5-10% IPC gain with clock regression is not at all surprising if I'll be honest. Just making the core wider and increasing total throughput, which appears to be what AMD has done, is actually a hilariously inefficient way to increase IPC on x86 due to register dependencies and memory/cache bottlenecks.

This is just wrong on so many levels. Both AMD and Intel CPUs have a massive register file and use register renaming to eliminate false dependencies. Adding more execution ports doesn't necessitate clock regression either.

I'm curious how you expect to improve IPC without being able to execute more instructions. The programs aren't going to change and branch predictors will never be perfect and caches cannot be any faster without decreasing in size. Wider cores are pointless if the rest of the CPU can't keep them fed, but Intel and AMD are aware of that and both have done a lot of work on their front ends as well.

People forget that Moore's law was taken out behind the barn and shot about a decade ago.

This is also wrong. It's still chugging along, with the only big change is that the costs for the new nodes aren't linear any more and have practically become exponential as well, meaning that the extra transistors we get aren't significantly less expensive.

You could perhaps argue technicality as the newest nodes aren't strictly reducing the feature size, but are instead employing other techniques to cram in more transistors, but we're still getting same effect. If anyone figures out a new SRAM design that allows for greater density, that would lead to significant reduction in die size as caches become larger.

 

[AMDK11]

Did you take this photo you pasted yourself or did you get it from somewhere?

 

[adroc_thurston]

If anyone figures out a new SRAM design that allows for greater density

Ain't happening till CFETs.
Until then, SRAM is dead.

Did you make this picture you pasted yourself or did you get it from somewhere?

I've said Chips and Cheese didn't I?

 

[AMDK11]

I've said Chips and Cheese didn't I?

Correct. I missed, or rather did not associate, the C&C abbreviation.

 

[AMDK11]

I still see very little reason to believe a 30-40% IPC uplift from either side (let alone more) is at all realistic in 2024.
To clear the air about my supposed partisan allegiance: I think Arrow Lake's going to be quite disappointing as well, and already called out Royal Core as essentially being Bulldozer with more money thrown at it.

Do we know exactly what RoyalCore was supposed to be?

It has been suggested (Exist50) that RoyalCore and LionCove may be the same project.

 

[DrMrLordX]

Enjoy the tears of disappointment and rage of everyone in this thread I will.

Watch Zen5 be significantly faster in SPECInt and electron crap while showing much less improvement in stuff like Cinebench. Everyone will declare their own predictions to have been accurate.

Correct. I missed, or rather did not associate, the C&C abbreviation.

Clearly that stands for Command & Conquer.

 

[adroc_thurston]

It has been suggested (Exist50) that RoyalCore and LionCove may be the same project

Who cares.
None of that is relevant to Intel's current IP roadmap.

Clearly that stands for Command & Conquer.

RIP my dear bestie.

 

[Joe NYC]

why.

ARLs are worthless memeparts.
Only LNL exists.

Any predictions if Zen 5 can match Apple M4 Geekbench 6 score that has been posted, in single thread? They seem to be continuously fudging Geekbanch 6, so not my favorite, but here it is anyway:

M4: ~3800
7950: 3068

 

[gdansk]

GB6? Only if Zen 5 has AMX. GB5 I think is possible.

Does anyone know if it has AMX?

 

[adroc_thurston]

Any predictions if Zen 5 can match Apple M4 Geekbench 6 score that has been posted, in single thread? They seem to be continuously fudging Geekbanch 6, so not my favorite, but here it is anyway:

Yeah it's not hard, but GB6 is worthless now since you can pump matrix matth subtest with shared accelerators.

Only if it has AMX.

Does anyone know?

It doesn't.
But it has the silliest, coolest AVX-512 implementation ever shipped.

 

[AMDK11]

Who cares.
None of that is relevant to Intel's current IP roadmap.

Maybe you don't care but I'm curious.

Nothing is known about RoyalCore and the name is just a name that can be changed or removed, just like that.