He's going to retcon it and say his sources meant Skymont.And it was 14%, bravo IDC.
If only you made those IPC claims about Skymont instead, they'd be right!
So Chadmont aside how does Zen 5 stack up against Intel's new P core?
About equal though Z5 has the far meaner FP implementation, though Intel's 2 level D-cache might do some funny things.So Chadmont aside how does Zen 5 stack up against Intel's new P core?
In mobile, yea.About equal though Z5 has the far meaner FP implementation
RWC is slower than RPC. By like 4%.LNC = RPC / RDC + 14% - clock speed regression
GB database has almost no controls and way too much noise. When Anandtech was giving us reviews every gen with Spec numbers, that was way more reliable. Unfortunately that is going away but I’d still take a known reviewer’s numbers over trying to get something trustworthy out of the GB data base.
I think these internal measurements be it powermetrics or the internal API geekerwan used are fine for measuring directional shifts *maybe* in CPU power, and just maybe, but overall they’re not that valuable.
To clear this up, I confirmed with someone who I believe can read Chinese (from Chips n Cheese discord) the reason for the different power figures we see — and indeed the 3.62W iPhone A17 Pro result & 7W M4 result — are because those were software modeled power using Apple’s internal APIs.
By contrast, Geekerwan has physically measured the A17 Pro (via removing battery and polling) and the power results are 5.7W minus all idle static/display.
I don’t believe M4 is doing 7W total at 4.4GHz ish (minus idle) by any means, it’s just bad software measurement. And given what we know about the iPhone measurements — the software 3.62W vs physically sampled 5.7W - a factor of like 57%, the true M4 system consumption being 11W ballpark makes total sense over the 7W as was measured by a leaker.
Knowing Intel, they will use up a lot of transistors to beef up the execution resources of their P-core. If they are able to learn well enough from the MTL lesson, they could end up having a pretty competitive overall performance against Zen 5, in almost everything except AVX-512.So Chadmont aside how does Zen 5 stack up against Intel's new P core?
Agree here. Apple pushing power is still a long ways from the levels Intel and AMD have or rather Intel did with their stagnation, because Apple is starting from a better base and can’t go too far anywayIt was around 5 watts for M1, it is around 7 watts for M4. Let's say 50% increase. Looks bad on paper, until we remember that these are sub 10 watt cores. I'd say they have a problem once they need to raise the wattage past 12 watts per core. Until then they are fine.
To be clear, the inconsistency part I was highlighting was namely that it is just measuring the CPU with software. I think you get that and acknowledge it but as you know, people tend to get antsy and won’t pay attention, haha. But yeah, the difference between the figures is just physical platform vs software CPU.Which is why compares across multiple results to quantify uncertainty. It works, even if the individual results are unreliable. There is no doubt that Anandtech results are more accurate per measurenment, they are still a single number which fails to capture the variability inherent to these tests. As I wrote on my previous post, just a slight fluctuation in operating frequency (which Andrei didn't sample and didn't report) can introduce a large relative error to IPC measurenments, making any comparison you do usig point estimates moot.
Besides, there is cross-device variability as well. To get a robust result you'd want measurenments of many different devices instead of repeated measurenments of the same device.
We definitely lack reliable tools to measure power consumption. Combine this with the fact different vendors report power consumption in different ways and it makes is very difficult to compare efficiency across devices.
My issue is that I am seeing very different numbers for A17 Pro reported by Apple APIs. I am an admirerer of Geekerwan's work, at the same time I feel like many of their reviews are rushed without proper analysis or methodology. The ~ 3.5W per core is close to what I'd expect of an average hybrid CPU workflow. That is not the peak CPU core power consumption as reported by powermetrics. But 7W for M4 is pretty much the peak (it goes higher, but the CPU doesn't sustain that for more than a fraction of a second) — at least on my personal devices.
Oh I believe it yaWhich is very close to what I see on my iPhone with powermetrics.
Yeah I know that. I’m implying it! think it makes total sense too. I’m saying we need to be conscious of that, because at least directional attempts at even comparisons are good, and now I’m seeing 3.62W and 7W being quoted @ Arm phones and QC laptops both measured from platform, and while Apple is meaningfully ahead — we’re seeing almost comically ridiculous comparisons being made even by people who frankly are biased against them, it’s just a mess.The 7W figure is not total, it's P-core consumption (sans uncore, RAM or anythign else). 11-13W platform at peak makes perfect sence to me.
That doesn't explain OEMs leaking super mega awesome SPECInt numbers.It feels to me like Zen5 as we see it today isn't the same Zen5 that was in the planning room three years ago. It seems like there were two plans: one plan for a successful roll-out of N3 and another that was a backup designed for N4. It looks like everything is getting the backup core. Not knowing how Zen5c behaves, I have no idea how it's going to shake out on N3.
Indeed...Who knew that the MLID slide from a year ago was dead on accurate. We just ignored it this entire time assuming it was too bad to be true.
I'm the one here who said there would have to be a Zen 5+ when TSMC 3nm becomes available in large quantities. The reason for it. Arrow Lake on 20A. Most people forget that Intel has a major node shrink coming. No more fake Intel generations. The efficiency gains by Intel will force AMD to move to 3nm before Zen 6. Wikipedia says that Zen 5 will be based on the fancy N4X. I doubt that. It was N4 and then N4P and now they say N4X. It's not 3nm but N4X is supposed to be the hotrod of 5nm silicon. I know they call it 4nm but it's still made on the 5nm process. They use 4nm to signify the advances in power, efficiency and density for more advanced cores than what standard 5nm can do.
The good news for AMD. They are releasing Zen 5 in July. They can say they are the market leader again in all segments for at least 3 or 4 months. A Zen 5+ (node shrink) would give AMD a big efficiency boost regardless of what Arrow Lake does in performance and efficiency. In my book, a CPU that sips power is better than a power hog performance queen. The caveat with Arrow Lake, they have a big efficiency jump coming with 20A. Intel has said 18A will bring a further 10% efficiency boost. The more advanced variant of 3nm TSMC silicon (not N3) will give AMD the efficiency to keep pace or better Intel.
@adroc_thurston , what do your industry friends say about the performance "regression" since everyone was expecting far more IPC from Zen 5.
but this feels like a backstab from Microsoft
The K models (unlocked multipliers) will have 125w TDP. The regular Arrow Lake CPU's will be 65w TDP. Zen 5 will be neck and neck with Arrow Lake with regards to power consumption. That's why 3nm would have given Zen 5 a decent edge in efficiency.will arrow lake actually release high-end models? all recent "intel node shrinks" i.e. "core ultra" have been weird low/mid-end models needing abysmal wattage to reach OK bench numbers
C&C on Xitter has a better shot of STX:
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And with annotations by Nemez:
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Same happened for Zen4 (and probably Zen3 too). I remember AMD released one number 13% something-something that caused the same crowd to implode (after hyping the release to death (in case of zen4)). Don't get the gloom, it's basically the same process, area size hasn't changed much, also there is no information on how bad it will OC/ work with RAM. Judging from very strange Intel slides (2c ulp vs 4c, PPW regression with increased package power) with no comparisons to the competitors' products, AMD isn't really in danger, if that's what people care about. I'd say Sierra Forest and its successors are more of a threat to AMD as compared to anything hybrid.hype train -> 16% "geomean" disappointment
I've advocated for P-cores and E-cores being really close neighbors in close proximity to each other or even next door neighbors with shared caches ever since the Alder Lake hybrid crap started. In the case of Zen5c, I suspect that it may not be technically or economically viable to mix and match cores created using different nodes with different densities on the same CCX. There might be ways to do that and who knows, maybe AMD and TSMC are in the research phase for that right now.And on the other, why not turn those middle Zen5c cores around and place them on the 16MB CCX with the big cores? Better performance, especially for games that scale well to 8 cores, which is a lot of them. Meanwhile the remaining 4 Zen5c cores on the 8MB CCX would still be more than sufficient for light and background tasks.
And also why they use it for zen5c.The K models (unlocked multipliers) will have 125w TDP. The regular Arrow Lake CPU's will be 65w TDP. Zen 5 will be neck and neck with Arrow Lake with regards to power consumption. That's why 3nm would have given Zen 5 a decent edge in efficiency.
Except that's not true I think? Is there really a case where NPU is being used heavily and the GPU also needs to be used at 100% capacity? Outside of maybe a game?