Hm, so it's 26% faster. Nothing too special. We know about 16% average ipc, so this is just a bench in the upper region. Why is everyone acting as if it was super high?!
Dropping the power can only be seen as a good thing. Like I've already said in the other thread, it's one of the few things we can use to gauge gains that are independent of benchmarks and testing conditions. If some Zen 5 SKUs drop power by about 40-50W when compared with Zen 4 counterparts, then they have to do so while offering at least the same level of performance. (they would have to offer more, but you get the idea) This means that Zen 5 will be significantly more efficient than Zen 4, which falls in line with the performance figures we've seen for Strix (like 40% higher perf with 50% more cores, this is only possible if core power is lower by about 35%)
The really weird and concerning part is the benchmark selection they presented us with, especially considering they will be launching these CPUs relatively soon and before the competition (so there's no point in hiding things from them at this stage). Even now, we have no way of evaluating 1T performance of Zen 5. It makes no sense, the opsec part is over.
You would think there is, but if you check the end notes for that slide... they say it's GB multi-core score. You can find the mobile slides here: https://www.anandtech.com/Gallery/Album/9476#25 (also be aware this slideshow contains the desktop endnotes as well, even though the desktop slides are in another article)There is this:
Their IPC figure is given for a mix of ST and MT workloads. According to their end note they were comparing at fixed clocks, but the SKUs chosen make no sense (9950X vs. 7700X) The problem with the benchmark mix is one cannot isolate MT or ST increase, it's a weird mix between the two.Are decreases or very slight increases in IPC likely for significant tests?
You would think there is, but if you check the end notes for that slide... they say it's GB multi-core score. You can find the mobile slides here: https://www.anandtech.com/Gallery/Album/9476#25 (also be aware this slideshow contains the desktop endnotes as well, even though the desktop slides are in another article)
Their IPC figure is given for a mix of ST and MT workloads. According to their end note they were comparing at fixed clocks, but the SKUs chosen make no sense (9950X vs. 7700X) The problem with the benchmark mix is one cannot isolate MT or ST increase, it's a weird mix between the two.
My headcanon is still that Mike Clark assumed 3nm, and maybe was counting on something on the order of 22% instead of 16% in that presentation. That would have been received a lot more positively.
My head hurts
AMD loves adhering to PPA metrics which is why some heads were lobbed off for RDNA3.It is quite peculiar that the die size of Zen 5 came to the same size as Zen 4
This makes the most sense, the alternative being 9950X vs 7950X. There are more typos/small mistakes in the slides though, making the keynote materials seem rushed.In the past, they have compared 16 core SKUs to 8 core SKUs at iso clocks but disabled one of the CCDs on the 16 core SKUs to match core count as well. I’m guessing the same thing happened here, they just forgot to mention one CCD was disabled.
AMD loves adhering to PPA metrics which is why some heads were lobbed off for RDNA3.
That is strange. The slide with the graphs literally says "Geekbench 6.3 1T". So that's false? Typo?You would think there is, but if you check the end notes for that slide... they say it's GB multi-core score. You can find the mobile slides here: https://www.anandtech.com/Gallery/Album/9476#25
They added close to 2B more XTors, that is a massive increase. (1/2 of 20B XTor minus the IOD)It is quite peculiar that the die size of Zen 5 came to the same size as Zen 4. As if there was a set ceiling on how big the die could be, and they were able to only put it so many features as they could fit. And some features were cut.
It is going to be a long time for us to get the theory validated - until Zen 6.
If you do that then you can't power down the bigger core cluster when you only need the smaller cores?
The opposite, you get it active and clocked low, like a ghetto.Otoh, you could probably power down the 8MB CCX pretty regularly.
It is quite peculiar that the die size of Zen 5 came to the same size as Zen 4. As if there was a set ceiling on how big the die could be, and they were able to only put it so many features as they could fit. And some features were cut.
I would argue it was a controlled, low yield tactical detonation. One particular poster is still trying to reconcile the data though.Oh, I see you guys blew up the thread (and the forum)! 🤣
And what advantages does it give? It'd be a scorching volcano for dual-sided sticks, there's no real benefit in mem speed as compared to proper 1dpc boards (if you look at these slides with 2dpc empty slot nubs), overall RAM size etc is the same as the current SS/DS sticksIntel apparently has some partners adding LPCAMM2 to boards. When compared side by side with a DIMM based board, the DIMM based board absolutely looks dated. Hopefully we see some action from the AMD camp, though I wonder if Zen 4/Zen 5 even support LPDDR5.
They added close to 2B more XTors, that is a massive increase. (1/2 of 20B XTor minus the IOD)
You can fit Zeppelin CCX (1.4B XTors) in there, just from the XTor increase
Zen 5 is not fully revealed, we will get more insights on the architecture and perf in a month or so.
Point being is they're not getting a real shrink here.You can spend the transistor budget on many things. Zen 4 got an enormous 7->5nm budget but didn't invest in IPC.
Point being is they're not getting a real shrink here.
All funky layout magick instead.