I think the point is not only allowing denser configurations, but IIRC these core are also optimized for a different frequency range (lower power than the regular Zen5 cores at low clocks) so they allow to save power in the configurations/situations when clock is not so high (idle, low load, high core count servers)What is odd is that the Z5c really has no significant size change. Looks like a Z5c is 75% of a Z5 (without L3).
I don't get the point of a compact core which only relies on physical optimization and cut down of things like L3 instead of an architecturally distinct design. They could have kept the FP width at 256, like mentioned in the leaked MLID slides.
Seems like a low effort attempt to me.
Please don't tell me you will pair the 9600 with A620M, running at DDR5-5600. Though if you have a 7600 then I suppose that would be fair.
What might those proper tests be, if you don't mind me asking? Can you share the post if you have posted results of these tests for some older CPU?
That is the covered by the physical implementation, like mentioned. Device characteristics influence leakage, frequency, area, efficiency, operating voltage, drive currents etc.I think the point is not only allowing denser configurations, but IIRC these core are also optimized for a different frequency range (lower power than the regular Zen5 cores at low clocks) so they allow to save power in the configurations/situations when clock is not so high (idle, low load, high core count servers)
RTL?That is the covered by the physical implementation, like mentioned. Device characteristics influence leakage, frequency, area, efficiency, operating voltage, drive currents etc.
N3E would offer much more differentiation with 2x1 fins vs 2x2 fins, but having a totally different RTL for c cores is what I am suggesting they should go for in addition to physical implementation.
I wonder what the clock speed loss is, when going from 2-2 fin -> 2-1 fin.Imagine the space savings a N3E Finflex 2x1 fin Zen5c core without the 512 data paths .
Oh certainly. I'm not saying all the oddities are negative. Just that they're oddities.Dropping the power can only be seen as a good thing.
It indeed doesn't make sense, that's why I'm so cautious.The really weird and concerning part is the benchmark selection they presented us with, especially considering they will be launching these CPUs relatively soon and before the competition (so there's no point in hiding things from them at this stage). Even now, we have no way of evaluating 1T performance of Zen 5. It makes no sense, the opsec part is over.
Possibly that was a plan but TSMC's delays on N3 process pushed AMD to do otherwise in the mobile/desktop area. Same capability core, moreover, should simplify scheduling.That is the covered by the physical implementation, like mentioned. Device characteristics influence leakage, frequency, area, efficiency, operating voltage, drive currents etc.
N3E would offer much more differentiation with 2x1 fins vs 2x2 fins, but having a totally different RTL for c cores is what I am suggesting they should go for in addition to physical implementation.
Imagine the space savings a N3E Finflex 2x1 fin Zen5c core without the 512 data paths vs vanilla Zen5.
Quite an easy task to make the IPC 20% for Marketing. Even I can do it. Just add these belowThere's just a lot of weirdness, so more than ever, I am eager to see third party reviews. I obviously don't expect 40%, but I wouldn't be shocked if we end up with a surprisingly decent number in the 20% range. 25% or more I don't think is happening.
To be fair to adroc, he didn't say IPC geomean. His prediction was for the SPECint benchmark and we don't know that yet.You wouldn't get rumours of +40% then it's 16%
Yeah sure but iterating through lists, tons of basic ops, basically all the core character/data/raw logic in any program will have massive INT requirements. It's necessary from boot all the way to shutdown for everything, with FP increasing in importance along with program specialisation/complexity.To be fair to adroc, he didn't say IPC geomean. His prediction was for the Specint benchmark and we don't know that yet.
Please share the links. Please *puppy face*GB 5.4 , two online results already show 21%, that too with a nerfed AES XTS score which incidentally was cited as +35% in the Computex info share
Maybe there is some SPECint subtest with a score massively inflated by Zen 5's architecture?INT logic is the core of all programs. So if you tell me +40% and we end up with say 35%, I'd say fine, but nowhere does it come close to 16%.
My point was that marketing could have gotten 20% easily and yet didn't.Quite an easy task to make the IPC 20% for Marketing. Even I can do it. Just add these below
Source on the weaker INT uplift?Z5 sees weaker uplift in int, the FP is a very solid uplift, similarly front end bound will see solid uplift
It's actually interesting that the 1T IPC numbers in one AMD barchart are lower than the nT performance uplift in the comparison with 14900k(s?), seems like either the frequency does not tank that much on Zen5 with multithreaded load as compared to Zen4 (5.1-5.2ghz on my 7950x3d with light sse loads, less than 5 Ghz in heavy AVX2 load), or maybe it's just "Intel (tm) (C) default profile" that tanks Raptor Lake MT resultsYou wouldn't get rumours of +40% then it's 16% BUT the power draw fell by a lot.
Please share the links. Please *puppy face*
| vs 7950X@2.3G | https://browser.geekbench.com/v5/cpu/22427061 | |
| https://browser.geekbench.com/v5/cpu/compare/22424015?baseline=22425328 vs 7950X@2.0G | https://browser.geekbench.com/v5/cpu/22424015 |
Z5 int uplift is quite moderate, around 16%, there is some bottleneck likely in the PRF or the scheduler. I would bet scheduler, this is AMD's first unified int scheduler since Z1 if MLID diagram is correct.Maybe there is some SPECint subtest with a score massively inflated by Zen 5's architecture?
Physical register filePRF?
I like what I see but bit confused.
The Z5 Strix frequencies are correct, see the .gb5 file if you have GB subscription or see the frequencies from BenchLeaks Twitter.Why is the 7950X showing lower frequency?
You can check the GB int sub scores, in my links above.Source on the weaker INT uplift?