Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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soresu

Platinum Member
Dec 19, 2014
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I do think Zen 5 will be great architecture relative to Zen 4 but it’s not some mythical core that will obliterate every other CPU microarchitecture for the next couple of years as some leakers touted it be. In that regard they already got proven wrong.
I think there is that, but I also think that AMD has provisioned its roadmap for the future so that there is enough room for improvement that multiple future core µArchs can build on Zen5, and still have something to show as a significant selling point rather than a bare minimum <10% avg gain.

It's no good managing some mind blowing, show stopping 30+% IPC gain for Zen5, only to produce a Zen6 or 7 looking so meager that people would rather put a pin in their upgrade, and wait for something more substantial to come along later.

With Zen1 they had no choice but to go all the way to dispel as much of the bad taste of Bulldozer as possible, but now they can afford to be a little more conservative, especially with Intel being so profligate with power spending to match or exceed AMD's efforts.
 

DrMrLordX

Lifer
Apr 27, 2000
21,797
11,143
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It's rare but it does happen. We had a GB leak last month for STX that was showing like a 70% IPC improvement or something if the reported frequencies were correct, which they obviously weren't.

Edit: there are now multiple STX entries on GB6 though which are showing roughly the same PPC, so it seems like, at least in GB6, STX has a much higher PPC improvement than 16%.

Or maybe it means that GB6 (and Geekbench in general) is a crappy benchmark.

Why it is AMD's fault when the performance doesn't meet some random forum user's expectation/fantacy ?

It isn't. They never leaked anything except maybe the slides showing +15% IPC. It seems that Zen5, being a new ground-up design, is going to have a wildly different performance profile than Zen4, such that it was never in AMD's best interest to hype the outliers when there may be situations where it isn't any better than +15-16% over Zen4.

One person told to me that the >40% zen5 uplift chips had a ton of bugs and could not be launched.

Does that mean we should expect bugfixed late-stepping Zen5 silicon? Or are we going to see massive performance gains in Zen6 from all the fixed bugs and other planned improvements to the core?

@soresu

Whatever is the power draw on Zen5, it looks to be lower than that of Zen4, at least on desktop.
 

Tuna-Fish

Golden Member
Mar 4, 2011
1,421
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And what's the significance of A0 silicon?

It means that the very first design AMD pushed to the fab worked, and didn't require any fixing. Usually when the fab sends the A0 back, it's broken and needs to be debugged and fixed. The A0 being a working, sellable part is considered a significant achievement for the design and validation teams, and saves months of work and tens of millions of dollars.

It's rare, but it does happen. IIRC, the last time it happened to AMD was Bobcat. It doesn't matter much for the consumer, other than that the product is out potentially a bit earlier.
 

soresu

Platinum Member
Dec 19, 2014
2,955
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One person told to me that the >40% zen5 uplift chips had a ton of bugs and could not be launched.
This kinda gels with my speculation that security vulnerabilities in the underlying µArch revealed during silicon bring up may have led to some loss in perf to half baked mitigation strategies.

Also a significant µArch shift to a much wider core is almost certain to bring a number of new errata into the mix, some of which very likely won't be fixed in the Zen5 generation.
 

branch_suggestion

Senior member
Aug 4, 2023
294
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This kinda gels with my speculation that security vulnerabilities in the underlying µArch revealed during silicon bring up may have led to some loss in perf to half baked mitigation strategies.

Also a significant µArch shift to a much wider core is almost certain to bring a number of new errata into the mix, some of which very likely won't be fixed in the Zen5 generation.
AMD has released multiple steppings of each Z5 part, so presumably they have gotten all they can by now.
 

static shock

Member
May 25, 2024
48
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AMD keep digging with the same(~) uarch wide won't take them back to the game.
Is pretty sad to see AMD doing record profits without a killer CPU core and a not so big GPU like the enthusiasts want.



At now everyone here know my real nick.
 
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adroc_thurston

Diamond Member
Jul 2, 2023
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This kinda gels with my speculation that security vulnerabilities in the underlying µArch revealed during silicon bring up may have led to some loss in perf to half baked mitigation strategies.
No.
Also a significant µArch shift to a much wider core is almost certain to bring a number of new errata into the mix, some of which very likely won't be fixed in the Zen5 generation
It does have some regressions, but not anything you should care about.
 

Kepler_L2

Senior member
Sep 6, 2020
460
1,895
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It means that the very first design AMD pushed to the fab worked, and didn't require any fixing. Usually when the fab sends the A0 back, it's broken and needs to be debugged and fixed. The A0 being a working, sellable part is considered a significant achievement for the design and validation teams, and saves months of work and tens of millions of dollars.

It's rare, but it does happen. IIRC, the last time it happened to AMD was Bobcat. It doesn't matter much for the consumer, other than that the product is out potentially a bit earlier.
But they did make B0 and C0 revisions, the question is 1)why weren't they released? 2)why did they wait 1 year+ to launch A0?
 

Abwx

Lifer
Apr 2, 2011
11,166
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But they did make B0 and C0 revisions, the question is 1)why weren't they released? 2)why did they wait 1 year+ to launch A0?

There s several dies, it could be Strix Point/Halo that required some respin,
is there an indication that it was the DT/servers chiplet that had revisions..?.
 

Abwx

Lifer
Apr 2, 2011
11,166
3,862
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9900X has a 1.4x MT throughput than 7900X on a 67W lower power limit?
Questionable.
7950X has 41% better score than the 7900X3D in CB R23, so that s relatively accurate, beside the 7950X doesnt get at 230W in CB and in any other bench.

One thing that is not logical is that if the 9700X does 25300 at 88W PPT then the 9950X should do 50000 pts since this would require only 180W, so far AMD slide state something like 46300 pts.
 

HurleyBird

Platinum Member
Apr 22, 2003
2,725
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You mean in tasks where you previously performed so well that CPU Z editor "updated" the bench to get Intel at the first place again under the pretense that Zen 1 was taking advantage of an alleged bug to score better..?..
If or until they "update" it again, yes, of course.
 

Thunder 57

Platinum Member
Aug 19, 2007
2,811
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What does Intel have to do with AMD slides?

Nothing. Try having a sense of humor.

if anyone is truly sandbagging it would be Intel this time. Their CPUs don’t launch till September with Lunar and October/November for Arrow. So it’s “okay” for Intel to use the margin of error.

I do think Zen 5 will be great architecture relative to Zen 4 but it’s not some mythical core that will obliterate every other CPU microarchitecture for the next couple of years as some leakers touted it be. In that regard they already got proven wrong.

I’m sure we will see some insane gains in AVX-512 but the actual core performance will have to revealed by SPEC.

Not really. If they don't know performance without a 20% span by now they are incompetent, or obscuring for some reason. Also, oliterate every other CPU uarch is some serious straw man crap. Nobody claimed that.

I think there is that, but I also think that AMD has provisioned its roadmap for the future so that there is enough room for improvement that multiple future core µArchs can build on Zen5, and still have something to show as a significant selling point rather than a bare minimum <10% avg gain.

It's no good managing some mind blowing, show stopping 30+% IPC gain for Zen5, only to produce a Zen6 or 7 looking so meager that people would rather put a pin in their upgrade, and wait for something more substantial to come along later.

With Zen1 they had no choice but to go all the way to dispel as much of the bad taste of Bulldozer as possible, but now they can afford to be a little more conservative, especially with Intel being so profligate with power spending to match or exceed AMD's efforts.

It's more in line with typical Zen gains. Mid double digits. Zen 3 was the outlier. People expected more because they (supposedly) widened the core for the first time. We probably won't find a lot until Hot Chips unfortunatly.

AMD keep digging with the same(~) uarch wide won't take them back to the game.
Is pretty sad to see AMD doing record profits without a killer CPU core and a not so big GPU like the enthusiasts want.



At now everyone here know my real nick.

Are you admiting to having a duplicate account on these forums? That wouldn't be wise.

18% ST 22% MT. Not bad. While disappointing compared to 40% dreams, it wasn’t long ago that 20% took 4 generations of 5%. Thanks AMD!

Nobody who knows what they were talking about expected 40%. Totally agree with the rest of it though. No more "You will get four cores with minimal IPC gains and like it*" nonsense. And no buying a new motherboard because we changed the socket just to screw you over and sell more chipsets.

* Want hyperthreading? Unlock it for an extra $100!
 
Jun 4, 2024
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Nothing. Try having a sense of humor.



Not really. If they don't know performance without a 20% span by now they are incompetent, or obscuring for some reason. Also, oliterate every other CPU uarch is some serious straw man crap. Nobody claimed that.



It's more in line with typical Zen gains. Mid double digits. Zen 3 was the outlier. People expected more because they (supposedly) widened the core for the first time. We probably won't find a lot until Hot Chips unfortunatly.



Are you admiting to having a duplicate account on these forums? That wouldn't be wise.



Nobody who knows what they were talking about expected 40%. Totally agree with the rest of it though. No more "You will get four cores with minimal IPC gains and like it*" nonsense. And no buying a new motherboard because we changed the socket just to screw you over and sell more chipsets.

* Want hyperthreading? Unlock it for an extra $100!
Oh, that joke was terrible lol
 

PJVol

Senior member
May 25, 2020
619
549
136
One thing that is not logical is that if the 9700X does 25300 at 88W PPT then the 9950X should do 50000 pts since this would require only 180W, so far AMD slide state something like 46300 pts.
Tip: CB R23
7900X 29,498 230W PPT (tdp 170w)
7900 25,260 88W PPT (tdp 65w)
 
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deasd

Senior member
Dec 31, 2013
553
867
136
It means that the very first design AMD pushed to the fab worked, and didn't require any fixing. Usually when the fab sends the A0 back, it's broken and needs to be debugged and fixed. The A0 being a working, sellable part is considered a significant achievement for the design and validation teams, and saves months of work and tens of millions of dollars.

It's rare, but it does happen. IIRC, the last time it happened to AMD was Bobcat. It doesn't matter much for the consumer, other than that the product is out potentially a bit earlier.
But they did make B0 and C0 revisions, the question is 1)why weren't they released? 2)why did they wait 1 year+ to launch A0?

My first thought is AMD believe A0 silicon is competitive enough and do not need any respin. I never heard this before for a DT chips. Last time I saw A0 chips was Cezanne which is Zen3 APUs happened in 1h2021.
I also heard B0 stepping Zen5 story but I guess this might likely become a refresh/Vcache thing to counter Intel in the future. There's still few months away from Intel's next gen product release.
 
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poke01

Golden Member
Mar 8, 2022
1,389
1,601
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Also, oliterate every other CPU uarch is some serious straw man crap. Nobody claimed that.

Okay maybe oliterate wasn't the right word but some here and on Twitter had much higher expectations about Zen 5 performance.

The above tweet implied that x86 vendors had a core that would considerably beat Apple in terms of IPC, assuming thats what is meant by the use of "lapped". We now that Apple increased IPC on average 8% over M3 which was released 7 months ago, so that whole tweet about regarding Apple's IPC is wrong too. Not to mention the advantage Apple has in perf/w and the existing IPC lead also wasn't taken into consideration.

So in what way did Apple get lapped at Computex?


Look, I'm not pointing this solely on one person but I think the lesson we can take is we shouldn't jump take leakers words as truth and make false assumptions as to why the performance wasn't as expected. The best thing we can do now is wait and see the results for Zen 5.
 
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