That's utterly ridiculous and completely untrue.Performance cores are in separate cache domain to efficiency cores. Pretty much similar approach as Meteorlake LPE-cores - they are only useful to save power when performance cores are totally shut off.
I think the inverse is true. The Zen 5c CCX is the most active and the 4C Zen 5 CCX turns on for bursty workloads. There is a video of Wendell from Level1Techs interviewing an AMD fellow who said this I think.Performance cores are in separate cache domain to efficiency cores. Pretty much similar approach as Meteorlake LPE-cores - they are only useful to save power when performance cores are totally shut off.
That's utterly ridiculous and completely untrue.
AMD 12 and 16 desktop CPUs also have multiple CCXs, the cores on different CCXs aren't useless.
So how long before we find out Strix Halo was restructured to have a 300 TOPS NPU and 2 Bobcat CPU cores
Dual CCX-cpu's aren't as useful as single cache domain cpus with similar core count. But that's not the same situation than with Strix point - in desktop both CCX has fast cores and equal amount of cache. In Strix point there's slow CCX and fast CCX with more cache but only 4 cores. AMD could do desktop cpu with one normal and one dense CCD to make similar situation but they probably won't even consider doing such a dog to shame desktop performance reputation. But they did it for mobile - after years of pretty flawless execution. Have to wonder if they are losing their mojo.
The fact that a single CCX can only support upto 8 cores seems to be a problem for AMD. More cores would require another CCX, and a seperate L3 block. Perhaps they should work on larger CCXes, or even do a rework of their core cluster hierarchy?
Regressing in the GCC subtest after all the accolades about that zero-bubble, 2-branches BPU with 16k L1 BTB... Jesus, this is Bulldozer vibes.Some very odd results, especially Specint in AT review. Zen 5 does look underwhelming considering AMD's claims.
Maybe they had to make two CCX instead of a unified CCX to power gate the zen 5 cores? I don't think they could turn off the zen 5 cores when idling without having put it on a different CCX. (Just a speculation)Turin dense is a 16-core CCX already. There's nothing fundamental that stopped AMD from putting everything on one CCX in Strix.
Exactly my thought. I will wait for desktop results but I'm starting to be quite concerned about the choices AMD made.Regressing in the GCC subtest after all the accolades about that zero-bubble, 2-branches BPU with 16k L1 BTB... Jesus, this is Bulldozer vibes.
Strix Embargo fell right now... lets read the articles
Yea, but somehow "the try new things core" got fkced up in good old AMD way.Exactly my thought. I will wait for desktop results but I'm starting to be quite concerned about the choices AMD made.
Can't blame people for being underwhelmed. I think they were expecting an M4 killerSeriously? 6 pages since 9am?
The cross-CCX latency is not nearly as big of an issue as some people make it out to be.
The lower clocks on the dense core cluster barely matter because the chip isn't able to run all cores at high clock speeds, and single threaded workloads will run on the fast cores anyways.
Cross-latency isn't problem biggest problem- being different cache domains is main problem. Have really, really wonder why AMD selected that CCX arrangement as it's the worst possible. They could have done 4+4 CCX with addtional 4 core low power CCX to have at least 8-core CCX with enough cache and fast cores for MT scalability. But they choose that - and result seems to be not that great.
So Zen5 = Bulldozer 2.0?
Fascinating.
So Zen5 = Bulldozer 2.0?
Fascinating.
Can you point to benchmarks from any reputable reviewer to show that this is an actual problem?
Thank you. I also had those statements still in mind but couldn't remember which interview it was. The interesting part about Zen 5c starts at 8m20s. Mehesh even envisions the separation of CCXs and thus cache contexts as beneficial for applications with different performance requirements. It just remains to be seen if these potential advantages will be leveraged in real usage.I think the inverse is true.
AMD went for the cheapest way possible as always...Cross-latency isn't problem biggest problem- being different cache domains is main problem. Have really, really wonder why AMD selected that CCX arrangement as it's the worst possible.
AMD went for the cheapest way possible as always...
Perhaps they really wanted to ensure perf/watt at the very start of the curve is competitive, so they increased the -C core count. I agree though, I'm confused about the P+E core arrangement too, and I'm really surprised out of the couple interviews with AMD employees we had, no one really asked them about this...Cross-latency isn't problem biggest problem- being different cache domains is main problem. Have really, really wonder why AMD selected that CCX arrangement as it's the worst possible. They could have done 4+4 CCX with addtional 4 core low power CCX to have at least 8-core CCX with enough cache and fast cores for MT scalability. But they choose that - and result seems to be not that great.
I guess we'll only know for sure with the release of Zen 7. It will be a dead giveaway if they revert some of their design choices.Yea, but somehow "the try new things core" got fkced up in good old AMD way.