Matches AMDs claims. They claimed 22% better MT in Blender which has 23% IPC. So in CB23 which has 17% IPC there should be a 16-17% uplift. 7950X scores 38.7k so it fits exactly.
Getting this result on an air cooler is impressive. 13/14th gen needs an aio
So regarding the 0% SpecInt improvement that AnandTech got, I think it would be good to put in context of the test setup they are using. They mention they are using WSL, but don't mention the type [WSL1 vs WSL2, with 1 being a sort of emulation layer, 2 being a VM running Linux Kernel, and the default nowadays] plus rather old Clang version. In comparison David Huang used native Linux environment and more modern version of gcc, but its worth noting that in both setups compiler will not generate AVX512 instructions afaik.
Now, why that might be important is if they are using WSL the core pinning might not work as expected so you might not measure what you expect to measure. Especially when dealing with hybrid architectures. I am not familiar with internals of Spec, but I would expect that 1T run should be pinned to the core either by spec runtime itself or by the person running Spec for meaningful results.
That plus difference in compilers used might explain why AT measures 7.01 Spec rate for Zen4 but Huang is seeing 8.45 for a core locked at 4.8 GHz if I understand his table correctly. Correspondingly he measures 9.27 for Zen5 vs 7.02 AT got.
Now I am just trying to understand why AT result is different than what other test seems to suggest [GeekBench INT improvement is also better than 0, especially the compiler subtest of geekbench that could be used as a proxy of broad integer workload stressing different parts of the core, is showing something in the ballpark of low but cositient improvement ].
The encoding test are also all over the place (looking at AV1), with there being large gap between Phoenix and Strix and then the difference gets swapped in the same test but different resolution? Feels like something doesn't quite work in the scheduling or in clock management. Could also be SVT having awful threading model perhaps.
I except that many workloads won't schelude right with that odd asymmetric CCX configuration. For games - limit them to 4 core CCX or results will probably be beyond terrible.
Hmm... ok... my bad then. The AMD specs for the Ryzen AI 375 is 15-54W.The STX in Asus ProArt can go upto 80W.
Come in here, and people are calling it "Bulldozer 2.0" and s**t posting everywhere.. what the hell happened to this place? , it's like Circus sometimes.
I'm amazed that this comment got jumped on (-7 downvotes? ).So Zen5 = Bulldozer 2.0?
Fascinating.
Not in the sense of being a completely uncompetitive product. It looks like AMD made some odd choices, tried some new tricks, and performance is kind of underwhelming, but it's not meaningfully worse than Zen4 on any axis and is better on some others.
Folks making the Dozer comparison need to remember that Intel was doing 50%+ more iso-clock ST int against it.
As you can see, my objective with the comment was to incite further discussion about those questionable architectural changes in Zen5. I had no ill intention of annoying anybody/trolling, but I admit my words were poorly chosen, and that may have inadvertently offended many people.Uhhh, no. No where near the same.
Since there has been made som z790 boards with camm2 slots does AM5 chips in theory supports camm2 modules or will it require a new CCD/memory controller and socket?
There are very few people in the media/online who can conduct proper SPEC tests and David is one of those people."I suggest you wait until I finish running SPEC and GB under Linux in a few days before drawing any conclusions.In addition, if you have read my previous analysis of performance bottlenecks, you will know that even for a 6-wide 4ALU x86 processor, the performance bottleneck is mostly not in the decoding width or the number of ALUs."
what's the point of bumping 8 Z4 cores to 12 Z5 cores if you're going to have the same perf
The performance at the same wattage is 17-34% higher. Notebookcheck compared against the Z1 Extreme and 8945HS:12 Zen 5+ Zen5C cores don't have the same perf as 8 Zen 4 cores.
certainly.Figures I've saw being throwed some time ago was around 170 - 180mm²
It comply with the Microsoft marketing point, it will be featured into newer designs and with more design wins, it will have a branding that indicates it's a new generation part
That I am not sure about. Phoenix/Hawk Point laptops have gotten much cheaper since they launched. And if Kraken is indeed 170-180 mm², then it's pretty much the same die area as PHX/HWK (178 mm²).and will also slot into a cheaper price bracket than HWK.
Am I the only one here who thinks that the Ryzen Z1 Extreme looks really good despite being an older generation? They need to get out some laptops with it. Maybe 20W max fanless ones.
It is a variant of the 7840U that was specifically optimized for very low wattage.the Ryzen Z1 Extreme looks really good
It should be only Turin-D.which of zen5 products will be on 3nm?
I corrected my post, I think it is only dense variant of Turin. Everything else is 4nm according to current information (but I might be wrong )Maybe Strix halo too?
Maybe AMD will release a microcode update to make use of that second decoder. Kind of like reverse hyperthreading but only for decodingseems like second decoder is not used in 1T.
AMD's Mike Clark gave interviews last week to Chips and Cheese and Ian Cutress. He said that practically all core resources can be used by a single thread.seems like second decoder is not used in 1T.
Certainly PBO or a manual OC though. If it achieved it at 230W, its so odd that AMD chose to require PBO to reach that perf instead of letting the proc handle it itself. Only thing I can think of is its a reliability/culpability play, and the voltage and current requirements to hit this ~45K are just not something they are comfortable having to warranty.Matches AMDs claims. They claimed 22% better MT in Blender which has 23% IPC. So in CB23 which has 17% IPC there should be a 16-17% uplift. 7950X scores 38.7k so it fits exactly.
So how would the 2nd decoder be used? It would decode the instruction immediately after the one being decoded by the first decoder?AMD's Mike Clark gave interviews last week to Chips and Cheese and Ian Cutress. He said that practically all core resources can be used by a single thread.
Aren't there some prominent rumours that Strix Halo has atleast one die based on N3E?I corrected my post, I think it is only dense variant of Turin. Everything else is 4nm according to current information (but I might be wrong )
Or that not all silicon may be able to do that reliably.Only thing I can think of is its a reliability/culpability play, and the voltage and current requirements to hit this ~45K are just not something they are comfortable having to warranty.