I dont mean any disrespect by this, you need to read about the difference between memory capacity and memory bandwidth.Allright then. There are still tasks, like 3D rendering, that does not benefit from faster RAM significantly, that would immensely benefit from additionaĺ cores. RAM speed perhaps becomes important factor when you run out of it and data needs to be fetched from drive, but thats better to be resolved by more RAM anyway.
Yes, keen to see the less power constrained reviews and wondering if there is a significant difference in binning. Could be a gen where AMD has lower costs per chip but a higher average cost of unit sold because the higher core count CPUs are less constrained overall.Looking over the variance in some of the reviews, I would surmise the lower TDP (65W) is hurting some results more than others.
Why? Because it looks like some boards are putting unnecessarily high voltage on some rails (e.g. vSOC 1.25V+) which would subtract that much more power budget from the cores.
Your uncore is a decent percentage of 65W (88W PPT) while at higher power budgets the percentage becomes less significant. Seeing 9600X hit higher clocks both ST and MT versus 9700X shows the lower power budget is really hurting Zen 5 reviews and crimping scores (esp 9700X). Or leaving a lot more OC headroom (20%+ in some cases!) depending on your perspective.
I expect to see this clarified a bit next week when we see what Zen 5 will do out of the box for the higher TDP parts, especially the 9950X.
Yeah, everyone knows to wait for:Current Sales at Mindfactory after 5 hours:
Not even 10 sold for both 9600X and 9700X.
No, I didn't miss a 0, it says "more than 5 sold" and next step would be "more than 10 sold".
I think he means to say that RAM speed is meaningless when the required data cannot be found in RAM. That's when the perceptible delay is felt. If more RAM allows more data to be held in RAM and prevents going to disk, then in that case, it's better to have more RAM than speedier RAM. This obviously is for limited cases where the application preloads the entire working set into RAM and then works on that exclusively, without needing to go to disk until the task is finished. He does have a point that speedier RAM may not help in limited RAM capacity scenarios.Ram speed becomes an important factor when you need the bandwidth. It's independent from memory capacity. The third sentence suggests you don't know the difference.
The chiplet crap and higher RAM latency will nullify any compute advantage it has.1. Arrow Lake
In 2027? worth the work? What if Intel doesn't want to lose more to AMD in performance and give IPC gains generation/year after generation.But they are
That is how sane TDP should look like. This could reduce cost of motherboards. People who wants to overclock are free to buy expensive motherboards.Seeing 9600X hit higher clocks both ST and MT versus 9700X shows the lower power budget is really hurting Zen 5 reviews and crimping scores (esp 9700X). Or leaving a lot more OC headroom (20%+ in some cases!) depending on your perspective.
The chiplet crap and higher RAM latency will nullify any compute advantage it has.
In 2027? worth the work? What if Intel doesn't want to lose more to AMD in performance and give IPC gains generation/year after generation.
BTW, i know some secret about the performance of Zen5 and Zen6.
Not all applications need highest bandwidth. That is why cache is there. Remember, each CCD will get its own L3. Even bandwidth limited multicore performance will be higher than 16 core parts.It would be a pointless product that nobody would buy. Partly because no one buys the 16 core chips anyway, but additionally because they would be severely bandwidth constrained. If you've read this thread you can see that the current chips seem bandwidth constrained as they are already.
It is easy to test if you are bandwidth limited. In best case, DDR5 can be read at 100GB/s. Say for simplicity 70GB/s. So for this to become bottleneck, your processing activity needs to be faster than this. For example, the application should be capable of encoding video at higher rate than this. Otherwise memory will not be a bottleneck for encoding. Same for other similar applications.I dont mean any disrespect by this, you need to read about the difference between memory capacity and memory bandwidth.
Ram speed becomes an important factor when you need the bandwidth. It's independent from memory capacity. The third sentence suggests you don't know the difference.
If you want to do things with lots of cores. AMD has a product for you. If you're a hobbyist that wants more than 16 cores but no commercial output to pay for it, tough luck. You can't have it without more bandwidth, the more bandwidth version is called threadripper.
Lets now compare the bandwidth that's available for a single CCDIf DDR4 is enough for 16 cores, I am sure DDR5 with double the bandwidth enough for 32 cores. At least should be enough for 24 cores.
For memory to become bottleneck, you need to process data faster than that. Most multi threaded tasks work less than this rate. Maybe apps like 7zip decode, it maybe a bottleneck.Lets now compare the bandwidth that's available for a single CCD
Single CCD Zen3: @ 1900mhz FCLK and 3800MT/s supersuper tight memory timings (this is pretty BIS with unstable OC)
View attachment 104834
Single CCD Zen5 @ 2200mhz FCLK + 6600MT/s
View attachment 104832
Single CCD Zen5 @ 2200mhz FCLK + 8000MT/s
View attachment 104833
Now tell me, do you still think its the memoryspeed itself that's the limiting factor here ?
When you have 50 or more individual benchmarks with bizarre performance profiles that don't match anything you do irl, it taints the geomean. Phoronix has been like this for years.
It's really just semantics. Every CPU carries over some design elements from previous generation. Even Zen used elements Carizzo, but I will say that Zen5 seems to be the biggest change to Zen yet. https://www.anandtech.com/show/1117...-review-a-deep-dive-on-1800x-1700x-and-1700/6Possibly moronic question but does Zen 5 qualify as an architecture or a micro-architecture?
There's enough changes in the frontend (and the back too to be fair) to completely change the performance expectations vis à vis the Zen 1 -> Zen 4 era.
It's just semantics but I'm not even sure if it qualifies as "reworking an arch" or "is a new arch" entirely. It feels very new to me.
For the power, AMD has taken what it learned with Carrizo and moved it forward. This involves more aggressive monitoring of critical paths around the core, and better control of the frequency and power in various regions of the silicon.
In general architecture is used for the instruction description (along with some system aspects) while microarchitecture is how an architecture is implemented by a CPU.Possibly moronic question but does Zen 5 qualify as an architecture or a micro-architecture?
Could be issues with how L3 cache is getting sliced up with more L2 connected to it.It really bothers me that the 9600x is almost 10fps faster than the 9700x in this bench by TPU. Even at different resolutions spiderman RT has an odd effect on the current Zen 5 CPUs. But also, for some reason this seems to be the only condition they tested that has this anomaly.
I guess my point was, you can have use for more cores without the need for more bandwith - as is clearly the case of rendering. In which case i dont need Threadripper, neither i am inclined to pay premium for it.I dont mean any disrespect by this, you need to read about the difference between memory capacity and memory bandwidth.
Ram speed becomes an important factor when you need the bandwidth. It's independent from memory capacity. The third sentence suggests you don't know the difference.
If you want to do things with lots of cores. AMD has a product for you. If you're a hobbyist that wants more than 16 cores but no commercial output to pay for it, tough luck. You can't have it without more bandwidth, the more bandwidth version is called threadripper.
May be a little OT, but i think that the ps5pro with rdna 3.5 plus rdna 4 RT means that the PS soc mean AMD will jump from there to RDNA5. Anyone that constantly saw amd putting their product roadmap got that the jump to RDNA3.5 next gen means that they are enforcing the personel and opening the money faucets for the RDNA5, a.k.a. the Zen of AMD GPUs.Counter point: I was also wrong about RDNA3 performance but right about Navi4c's cancellation.