No link to the review..?
This 9700X curve can be right only if the idle power is much higher than the one of the 7700X, hence the apparent low efficency at low power, as said provide us a link so we can chek what it is about.
Are there any gaming tests spevifically with RT on, in games like Cyberpunk or Those spiderman games, or control…. I recall there were people here who claimed this was achilles heel to Zen4, the vanilla ones at least, compared to Intel, so it would be good to see if there is any improvement.All you armchair experts saying Zen5 stinks at gaming, explain the .1% lows away
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Thanks for the link.I posted it last page but I will post it here again.
His screenshot is taken from 7:04
Zen 5 is basically in parity with Zen 4 going below 75W. There's the answer.
This guy also briefly mentioned the fact that DDR5-6000 is crippling Cyberpunk 2077's performance.
PPT limit of the 7950X is 230W and under sustained heavy MT workloads, it tends to sit around 215-225W due to hitting thermal limits (vs. Sitting closer to or hitting 230W PPT limit). The graph appears to show ~200W, which seems like it would be in the neighborhood of core only power.Problem is that Computerbase has this for CB 2024, someone said that it could be the cores power wthout the uncore but from the 7950X review it s clear that they measure the whole package power.
That someone was me. And yes, they usually measure package power, but for that specific measurement they only measured the cores. It's described in the text. How about just using auto-translate:Problem is that Computerbase has this for CB 2024, someone said that it could be the cores power wthout the uncore but from the 7950X review it s clear that they measure the whole package power.
No, there s peaks over 200W, beside the CPU use only 189W in Handbrake wich is the app used for this test and 196W in Prime 95, from their measurement at the main power in Cinebench can be estimated accurately at 215W peak at most.PPT limit of the 7950X is 230W and under sustained heavy MT workloads, it tends to sit around 215-225W due to hitting thermal limits (vs. Sitting closer to or hitting 230W PPT limit). The graph appears to show ~200W, which seems like it would be in the neighborhood of core only power.
That someone was me. And yes, they usually measure package power, but for that specific measurement they only measured the cores. It's described in the text. How about just using auto-translate:
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And yes, I still need to point out the "four cores" mistake to them. That's 8 cores for all the lines.
Wow that's mid. Again, I can not wait for that spec2017 int power curve lol.That someone was me. And yes, they usually measure package power, but for that specific measurement they only measured the cores. It's described in the text. How about just using auto-translate:
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And yes, I still need to point out the "four cores" mistake to them. That's 8 cores for all the lines.
This is exactly my thoughts. Zen 5 seems to have been architected to take advantage of N3, while simultaneously being designed to work on N4. Its quite odd, and as a matter of fact, I cant think of any other CPU that was simultaneously designed and released (yes, Turin not out yet released but running in labs and sampling) on two fully different process nodes.It seems to be an architecture that is a bit big for its boots, or at the very least not optimised for the node. Reading between the lines in various interviews it did seem that's what Engineering would have liked exclusivity on N3E
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This curve matches some of the data from early 9950X testing.
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Seems the knee of the curve for Zen 5/N4X is both higher and less aggressive than Zen 4 on N5(p) It's easy to say N3E won't help much, but doesn't need much. Shifting that curve to the left is all. The fact it's still scaling suggests it really does need to be on a better node.
Still have to wonder why a higher TDP point wasn't selected for the 9700X , Is there voltage limit issues pushing higher TDPs on this node? it would also explain the max ST boost clocks pretty stagnant. Has anyone been able to push these higher yet?
Not going to happen. Strix Halo might be able to do something like that with its 3nm IOD and new chiplet packaging, but its designed for LPDDR so I dont know if its even technically possible to release on a desktop package and work with DDR5.
Not very encouraging. Hopefully the EXPO 8000 MT/s kits will have lower timings than the ones for the kit used by Larabel.
I really want AMD to pull some miracle with an updated IOD that allows the X3D chips to use DDR5-8000 in 1:1 mode.
This is exactly my thoughts. Zen 5 seems to have been architected to take advantage of N3, while simultaneously being designed to work on N4. Its quite odd, and as a matter of fact, I cant think of any other CPU that was simultaneously designed and released (yes, Turin not out yet released but running in labs and sampling) on two fully different process nodes.
The reason why 8000MT is doing little to nothing is the number of GMI links. Single link is the bottleneck for throughput. So going with higher kits will make sense only for dual chiplet SKUs. And 1:1 mode is less important for x3D SKUs because they have the 3d cache to insulate from DRAM latency.
Not very encouraging. Hopefully the EXPO 8000 MT/s kits will have lower timings than the ones for the kit used by Larabel.
I really want AMD to pull some miracle with an updated IOD that allows the X3D chips to use DDR5-8000 in 1:1 mode.
If you want to show off your memory, now or in the future you still have to buy a completely different AMD CPU. Latency or performance aside, a classic Zen4 or Zen5 CPU outside of the G series can't even move with 10600mhz DDR5 memory.
Not very encouraging. Hopefully the EXPO 8000 MT/s kits will have lower timings than the ones for the kit used by Larabel.
I really want AMD to pull some miracle with an updated IOD that allows the X3D chips to use DDR5-8000 in 1:1 mode.
If the redesigned core lets the 3D cache models run @ full speed 5.5Ghz then it will be ~15% better performance than the 7800X3D.
Not very encouraging. Hopefully the EXPO 8000 MT/s kits will have lower timings than the ones for the kit used by Larabel.
I really want AMD to pull some miracle with an updated IOD that allows the X3D chips to use DDR5-8000 in 1:1 mode.
In fact, the AVX512 improvement on Zen5 created a memory bottleneck so large that it became the primary reason why I promoted the BBP mini-program from a tool for verifying Pi records to a formal benchmark. The regular benchmarks wouldn't do Zen5 (and future processors) any justice. At least until someone can figure out how to get DDR5-20000 on AM5...
How many? And which of these are you running once a month or more often? Thanks in advance.There are many MT workloads that don’t require that much memory bandwidth.
One could show them just how big the dies are and how 9950X looks under the lid, yet they would still keep bringing this up regardless.They won't be launching higher count CPUs on AM5. Broken record but people keep suggesting an idea without merit
Couldn't they do something about the placement of these components (resistors?) to squeeze one more die in there?One could show them just how big the dies are and how 9950X looks under the lid, yet they would still keep bringing this up regardless.
Just keep in mind, that you need both CCDs active to see the improvement in Mem BW. Because each CCD has only one active GMI link to IOD. But the CCD itself has two GMI interfaces [at least this was the case with Zen4 and this was a reason why some lower core count SKUs had 2 links enabled, to ensure they could better tap into socket's bandwidth].Good information, y'all!
@MS_AT , thank you for filling me with hope for the 9950X with DDR5-8000 Can't wait to see the Phoronix benchmarks for that!
@Asterox , so DDR5-8000 kits will be more beneficial for Zen 5 desktop APUs!
From http://www.numberworld.org/blogs/2024_8_7_zen5_avx512_teardown/:
DDR5-20000 would have about 310 GB/s of bandwidth.
Guess which upcoming part has that much bandwidth on tap?
STRIX HALO!!!!
Now if AMD doesn't cut the AVX-512 width in that part, we are in for a REAL performance revolution!
Not going to happen. Strix Halo might be able to do something like that with its 3nm IOD and new chiplet packaging, but its designed for LPDDR so I dont know if its even technically possible to release on a desktop package and work with DDR5.
Easiest and largest performance gain for AM5 is maxing tREFI out at 65k for all memoryspeeds
Not very encouraging. Hopefully the EXPO 8000 MT/s kits will have lower timings than the ones for the kit used by Larabel.
I really want AMD to pull some miracle with an updated IOD that allows the X3D chips to use DDR5-8000 in 1:1 mode.
During the course of our testing, we observed that Windows 11 was scheduling workloads on the 9700X in a manner that would try to saturate a single core first, by placing workloads on each of its logical threads. Additionally, the placement would put load on the CPPC2 "best" or "second-best" core (gold and silver in Ryzen Master)—which makes sense. However, if a highly demanding single threaded workload runs on one core, scheduling another demanding workload on the second thread of that core will result in lower overall performance. It would be better to place them on two separate cores, where they each have access to the full resources of that core. We hence set out to see if this is an SMT-specific problem.
I think I read in some online posts that higher tREFI can result in hotter DIMMs. Is it possible to do 65536 tREFI without special cooling on DIMMs?Easiest and largest performance gain for AM5 is maxing tREFI out at 65k for all memoryspeeds
Sadly it seems like very few reviews understands this 🤷♀️
Runs fine even on naked DIMMsI think I read in some online posts that higher tREFI can result in hotter DIMMs. Is it possible to do 65536 tREFI without special cooling on DIMMs?
If anything, I'd think it would run the dimms cooler. All it does is increase the time between refreshes. Fewer refreshes = less power = cooler, maybe?I think I read in some online posts that higher tREFI can result in hotter DIMMs. Is it possible to do 65536 tREFI without special cooling on DIMMs?