$$$?So AMD had about 2 years after Zen 4. That wasn't enough for them to take DDR5 seriously and develop a decent IOD???
I think there's something AMD isn't telling us.
For gaming it'll have to be Zen 5 X3D variant or 7800X3D. Vanilla Zen 5 for gaming build is just pointless with 7800X3D around.
This is basically what you can expect out of a 105w TDP 9700x. The gap has now been widened from 5% to 15% against 7700x (CB), but efficiency is out of the window, unfortunately. So technically 16% IPC isn’t entirely wrong at iso power, the main concern for most of us is it just isn’t showing in gaming. Power limit it to 65W and reduce the price, there goes the non X and everyone is happy.
As a general rule, you cannot call any information wrong, unless you can prove it is wrong.
To make it fast you would need to have something like Rosetta. Recompile at first run. Then you would need sophisticated logic that would be able to figure out data flow and data dependencies as repacking 128b AVX2 ops into 128b AVX512 ops would give you no performance uplift for arithmetic operations. New instructions available from AVX512 could make some things more efficient providing that the transpiler would be able to guess intent from the disassembled code and deploy more efficient constructs. And since the code was most likely tuned for the hw that was lowest common denominator during game development the data layout could make it so that nothing more than 128b to 128b would be feasible most of the time.Games could be made to work better on Zen 5 if only there was a way to load a game executable and translate all the AVX2 128/256-bit instructions to 512-bit AVX-512 ones. I know, there are probably a million reasons why that's not possible but if only it were...
How about kind of a VM hypervisor thingy that traps the AVX2 instructions and translates them to AVX-512 ones? It may not enhance all games but there could be cases where the overhead of translation is overcome by the speed improvement.
Do you mean those 1 cycle instructions that now take 2 cycles to complete? That's the only regression I know of on Granite Ridge and it applies universally to all SIMD instructions. And seems that X264 subset of SPECInt doesn't seem to care much. Benchmarks done by Phoronix with AVX512 disabled also don't show terrible picture.The regression in some SSE/AVX instructions, which a lot of real software actually uses, is probably even more serious.
In that case, generate executables with a launcher that uses CPUID to detect AVX-512 instruction availability and uses the appropriate executable. Yes, there might be multiple AVX-512 binaries needed thanks to Intel's fragmentation mess but games are multi-gigabytes in size anyway.And since the code was most likely tuned for the hw that was lowest common denominator during game development the data layout could make it so that nothing more than 128b to 128b would be feasible most of the time.
Yes. AFAIK there is only autovec in SPECint? So I wouldn't expect it make any impact there.Do you mean those 1 cycle instructions that now take 2 cycles to complete? That's the only regression I know of on Granite Ridge and it applies universally to all SIMD instructions. And seems that X264 subset of SPECInt doesn't seem to care much. Benchmarks done by Phoronix with AVX512 disabled also don't show terrible picture.
WRONG. Simple as that.The burden of proof is on the the party that states something, not everyone else to prove them wrong.
Sure, but once again to make full use [this 2x throughput boost we get with Zen5] they would need to design the whole game with this in mind, otherwise throughput wise you would not see the speed up you would like to see. Not to mention the code duplication for the parts they had to hand-tune because autovectorizer was unable to produce sensible code. So validation time will increase and all this effort for relatively small user baseIn that case, generate executables with a launcher that uses CPUID to detect AVX-512 instruction availability and uses the appropriate executable. Yes, there might be multiple AVX-512 binaries needed thanks to Intel's fragmentation mess but games are multi-gigabytes in size anyway.
Precisely and the autovec will be able to handle simplest cases like arrays sum or reductions and those would be using int adds or substractions that got hit by the regression. But I don't have instruction trace, so I am just happily guessing.Yes. AFAIK there is only autovec in SPECint? So I wouldn't expect it make any impact there.
Exactly, and even with those regressions Zen5 is faster than Zen4. In the geomean for AVX512 disabled Zen 5 enjoys 15% lead. Of course you can find outliers where Zen4 is faster but those are relatively minor differences.And why would disabling AVX-512 have any impact? The regression exists even on the 256-bit versions of Zen 5.
WRONG. Simple as that.
If somebody says something, it is in his best interest to support veracity of the statement as best as he can. Sometimes it is not possible to do so.
Is somebody else wants refute veracity of the statement, he must PROVE IT to be wrong.
WRONG. Simple as that.
If somebody says something, it is in his best interest to support veracity of the statement as best as he can. Sometimes it is not possible to do so.
Is somebody else wants refute veracity of the statement, he must PROVE IT to be wrong.
View attachment 105531
The only party able to refute the claims contained above is AMD, for example by publishing detailed and complete information about the ZEN 5 development project.
Zen4 returned $3 per day in avx-512 miningAvoid dual CCD Zen 5.
It'll probably hurt bad in the countifs and other similar multithreaded formulas.
This is basically what you can expect out of a 105w TDP 9700x. The gap has now been widened from 5% to 15% against 7700x (CB), but efficiency is out of the window, unfortunately. So technically 16% IPC isn’t entirely wrong at iso power, the main concern for most of us is it just isn’t showing in gaming. Power limit it to 65W and reduce the price, there goes the non X and everyone is happy.
Getting off topic here, but you will find DEI is part of a broader global strategy under the umbrella term "ESG". Nvidia & AMD are rated (among others ) as top performers in this concept according toOK, we maybe have a new explanation for the Zen 5 disappointment.
DEI hires!!!
/s
So, when will I be able to accept my accolades? I was right about everything with regards to Zen 5, but people didn't want to listen to Cassandra.
Fmax wrong by 600MHz. IPC wrong on both SPECint (11%) and on SPEC fp (23%). You are awarded no points. Neither of your predictions were close.So, when will I be able to accept my accolades? I was right about everything with regards to Zen 5, but people didn't want to listen to Cassandra.
Maybe subsequent Zen releases such as Zen6 will be based on e.g. Zen4 instead of Zen5?I wonder how many engineers will need to work on this "flopper" even after its release to make it less bad. It may have flopped many times already during the development.
I would like to remind the pessimistic people here that Zen 5 is still the best Excel processor out there.
Logic fail. You make the claim, you supply the evidence. Veracity is irrelevant.WRONG. Simple as that.
If somebody says something, it is in his best interest to support veracity of the statement as best as he can. Sometimes it is not possible to do so.
Is somebody else wants refute veracity of the statement, he must PROVE IT to be wrong.
Could be related to being laser focused on Turin development, leaving the less experienced engineers handling the desktop part and just barely making it work.The inter-CCD latency problem may be somehow strongly related to some hardware flaw or peculiarity, which will make fixing it impossible or very difficult.
Zen 6 is probably almost finished.Maybe subsequent Zen releases such as Zen6 will be based on e.g. Zen4 instead of Zen5?
Since MLID said the Zen5 design was based on the Zen2 codebase (due to a decision by the Zen5 team), shouldn’t that be possible?