Why would it? N6 is only ever worth it for pure SRAM and HSIO applications in this day and age.
Why would it? N6 is only ever worth it for pure SRAM and HSIO applications in this day and age.Strix Halo notably doesn't seem to be using any N6.
How do you not know what System Level Cache is. I am amazed.Which means?
Is this separate from L1/2/3?
Sounds like it's basically just a different name for eDRAM.How do you not know what System Level Cache is. I am amazed.
System Level Caches are used in SoCs (which combine different components like CPU, GPU, NPU, ISP, Media Engine, Display Engine etc..). The System Level Cache is the last cache level on the chip (after which is DRAM), and it is a common cache that can be accessed by any of the subunits in the SoC.
The system level cache is just SRAM. It's sometimes called the LLC (last level cache). Apple's SOCs and most android SOCs have one. It can be used by GPU, NPU, and other coprocessors, whereas L1, L2, and L3 can generally only be used by the CPU.Sounds like it's basically just a different name for eDRAM.
Unless it is actually SRAM?
Sounds like a perfect candidate for SOT-MRAM to replace if so.
It stands for Spin-Orbit Torque Magnetic RAM.I haven't heard of SOT-MRAM, but I'm skeptical of new memory technologies. It seems like one pops up every year.
Sounds like it's basically just a different name for eDRAM.
Unless it is actually SRAM?
Sounds like a perfect candidate for SOT-MRAM to replace if so.
It stands for Spin-Orbit Torque Magnetic RAM.
It's an evolution on STT-MRAM, which is currently the only significant MRAM type in production I believe.
It's not quite as fast/low latency as SRAM, but it's very close, and unlike SRAM it is non volatile.
Unfortunately the current iteration is similar in area to SRAM, which is not very helpful.
The coming VGSOT-MRAM further improves it by switching to purely voltage switched write operations, which allows a much smaller cell.
I haven't heard of SOT-MRAM, but I'm skeptical of new memory technologies. It seems like one pops up every year.
I think that is the pre STT-MRAM device tech with the same interface as toggle NAND, so it scans that volumes would still be larger for that.AFAIK toggle MRAM volumes are enormously higher than STT-MRAM.
Why would it? N6 is only ever worth it for pure SRAM and HSIO applications in this day and age.
Most of the acronyms are pretty straightforward (the S and 2nd T is STT and SOT are both spin and torque) when you learn spintronics terminology.Agreed. They acquire more letters in their acronyms as time passes, but I'm still waiting to see one that has any chance of becoming something more than a niche.
Standard processes are becoming less of a constraint as the chiplet paradigm evolves with ever increasing interconnect density.If one appeared that did promise to be a real and fully scalable alternative to SRAM and worked with standard litho processes
No?There is a plenty of IO, analog, SRAM in, say Strix Halo SoC.
Ugh no, their core IP is just good.AMD competitive advantage has been chiplets and 3D stacking
Yep, feel the same as Doug. I mean, eventually if something does come, there might be a very slight lag time from R&D to an early use, but we’d see at least someone using it early on or investing in it. Not seeing that with any of this stuff. (Tsv cache aside)Agreed. They acquire more letters in their acronyms as time passes, but I'm still waiting to see one that has any chance of becoming something more than a niche.
If one appeared that did promise to be a real and fully scalable alternative to SRAM and worked with standard litho processes, then you'd see Intel, TSMC, Apple, Qualcomm or AMD move to acquire them and gain that advantage to themselves.
The same baseline tech was used to develop advanced hard disk drive heads, so actually the tech is very old and very much the opposite of niche.
No?
It barely has any PCIe and it's a power-sensitive part aka caches over 2.5D is a no-go.
Ugh no, their core IP is just good.
Other voodoo is icing on the cake.
Mostly the lack of I/O is because the PCI-E x16 for the GPU are routed internally towards the integrated one, as this part is not developed for the use with an external graphics card. As this is a laptop part (even if premium ones) the amount of residual I/O is probably considered as more than enough for that class of devices.Maybe there is only a limited I/O and analog because SoC is an expensive N3 silicon.
Maybe, if given some ~75 mm2 of M2, the designers would go wild with IO, including networking all sorts of USB / Thunderbolt.
This along with memory controllers and 64 to 128 MB of SLC.
In theory, the Strix Halo successor could break up the SOC die into 2 dies - N2 or N3 and N6, each ~150 mm2, 3D stacked. Each die (on its node) would minimize its disadvantages and maximize its advantages.
Probably, but as said a discrete GPU will defeat the purpose of such an APU. At that point, better focus on a Fire Range laptop which would be noticeably cheaper and it would have more available PCI-E lines if someone really needs those in a laptop.PCIe x8 is enough for most laptop dGPUs, no?