There's not much of a point in going beyond RDNA 3.5 on their APUs for another generation or two due to RAM throughput limitations. Anything that's going to push iGPU performance much past the incremental upgrades we've seen in the latest products (excluding Strix Halo, which gets a wider memory bus) won't have much of an impact as RAM throughput will only go up a little (percentage wise) in the next two years or so, at least until DDR6 makes mainstream release.
The only end-around for this would be integrating infinity cache/MALL cache/SLC or whatever it gets called onto the APU. That is technically doable now, and is being done with Strix Halo, but isn't fiscally sound yet. When TSMC gets N3P, N2 and further generations ironed out, and we get N4C based 3D cache dies to stack with, then we might begin to see products take advantage of greater bandwidth available by moving to notably higher iGPU configurations.
That being said, Strix Point with their 8 WGPs and likely with LPDDR5X running north of 7800 speeds should be suitable for high detail 1080p gaming without having to lean too heavily on scaling technologies, and with scaling tech, should be able to run the highest detail settings with good results at 1080p while also offering playable quality with modest detail at 1440p. We won't see extensive ray-tracing in iGPUs for some time, though, the limited ray tracing capabilities that are there now can provide some modest image enhancements already if they are carefully applied.
To make this relevant for the Zen6 thread, I think that AMD may investigate using 3d stacked cache for the Zen6 version of the Strix Point product segment. I could see using the increased circuit density for another pair of WGPs, going from 8 to 10 or maybe even 12. RAM wouldn't keep up though, so I think that a smallish 16MB N4C based 3dCache implementation option on it would bring notable results.