There should be some, even if small, clock speed uplift. If from nothing else, then from new process technology, which will likely be one of N3 variant. Maybe either N3E or N3P
Doubt there will be increased clock speed. What's more likely to help Zen 6 is IOD and GMI redesign.
For me the SoC design is what is more interesting, been a long while we have been discussing about the GMI replacement.Doubt there will be increased clock speed. What's more likely to help Zen 6 is IOD and GMI redesign.
So how will fare Zen6 ST uplift?
Smaller IPC gain than Zen4 -> Zen5, but coupled with clock speed boost thanks to N2...
Medusa Ridge
Medusa Point
Medusa Halo
16 for Ridge and Halo, 12 for Point. Same as this generation. There's been no indication that AMD wants to increase core counts on client next genAny speculation on Core Counts for these?
Most likely Medusa Point 2, but it's really too early to say anything ¯\_(ツ)_/¯ because I think It's a 2026-2027 productWhat will the Kraken Point counterpart of Zen6 be called (if there is even one)?
With the Clash of the Titans theme of Kraken and Medusa maybe it's called Calibos or something similar 😅What will the Kraken Point counterpart of Zen6 be called (if there is even one)?
Cerberus codename was already used (Zen3 core).With the Clash of the Titans theme of Kraken and Medusa maybe it's called Calibos or something similar 😅
Or it could just be Greek monster themed in general.
Like Typhon, Scylla, Charybdis or Cerberus to name just a handful.
Plus Persephone and Morpheus for Zen 4 and 6 cores.Cerberus codename was already used (Zen3 core).
Perhaps Strix Halo being slotted between Zen 5 and 6 is not so much about testing, but more about time to market.The rumor that was passed around on this forum was that Zen6 was more about the package stacking/connection tech upgrade and that Strix Halo was effectively a test product for part of that. Reading about the CCDs essentially being swappable maps to that well.
"Phenom X8" was codenamed Hydra, IIRCHydra is obviously another big Greek monster name.
That never happened though right?"Phenom X8" was codenamed Hydra, IIRC
Yea, the "X8" was probably just a hoax. Who knows.That never happened though right?
AFAIK it only went up to X6 with Thuban.
Well, ye but no.One thing I would like to emphasize is the amount of die area that can be saved on the CCD by changing the interconnect technology
So you are basically saying, that the area saved by much denser bumps is entirely eaten up by more complicated Control-Logic?Well, ye but no.
Unfortunately the more complicated a data signalling method is to extract greater bit/watt efficiency, the more complicated the circuitry is likely to become and therefore the area it takes up on die.
Best case scenario they can somehow exploit vertical layering in the future to punt the major IO off the main core layer onto its own layer, much as there is a possibility to take the L2 and L3 completely off the main layer of a stack as vertical interconnect density increases.
The other possibility is photonic IO, but it remains out of reach at this level of transistor geometry as the wavelengths of light far exceed the scale of cutting edge transistors making downsizing optical components extremely difficult.
Sure thing.Maybe you have a good example to support this?
How does this compare to the case discussed here - apart from generally also having something to do with communication?Sure thing.
Just look up 10G-BaseT ethernet.
It's been around for something like 18 years and it still stinks because the complexity of the signalling makes it so expensive per port in power.
One would assume that increasing the number of interconnect microbumps (or whatever the evolution is called) allow them to widen the IO and hopefully make it less complex.How does this compare to the case discussed here - apart from generally also having something to do with communication?