One thing I would like to emphasize is the amount of die area that can be saved on the CCD by changing the interconnect technology. The following picture is from the MI300 deep dive:
On the right picture, you can see the SoIC Interfaces represented as two tiny blue boxes.
The currently used GMI links for all of their CPUs are the two big orange blocks left and right of the left box.
Now, although we know, that SoIC is a lot more dense than for example InFO-RDL, even the latter will help them on saving a lot of die area for IO. This could either be used for cost benefits or could (hopefully) be put to good use for performance. And should Zen6 be produced in N3 as expected, these savings are even more significant as in N4.
On that note I am also very interested in comparisons of Zen5 and ARL regarding how much die space gets spent only for interconnects. I would expect ARL to fare better in that regard.