Question Zen 6 Speculation Thread

[Tuna-Fish]

Well, ye but no.

Unfortunately the more complicated a data signalling method is to extract greater bit/watt efficiency, the more complicated the circuitry is likely to become and therefore the area it takes up on die.

Works the opposite in this case. The advanced packaging methods get better data rates because of better signal paths and denser (hence, wider) interfaces. This means that the complexity on the signaling side goes down.

Just look up 10G-BaseT ethernet.

It pushes 10Gbit over 4 twisted pairs over a distance up to 100 meters, using basically black magic. The interfaces we are talking about here are very wide (think 512 bit or so), simple single-ended signaling over a distance of less than a millimeter.

 

[soresu]

It pushes 10Gbit over 4 twisted pairs over a distance up to 100 meters, using basically black magic. The interfaces we are talking about here are very wide (think 512 bit or so), simple single-ended signaling over a distance of less than a millimeter.

I was using an example of signalling bloat when he asked for one.

Nothing more relevant came immediately to mind.

But ye, black magic might as well be the case from my laymans reading of it 😂

 

[blackangus]

I cant wait for sound wave to transform my mobile experience.

 

[FlameTail]

I cant wait for sound wave to transform my mobile experience.

You'll be waiting a long time, I guess.

 

[BorisTheBlade82]

Wrong thread - please ignore/delete

 

[Panino Manino]

If 4-Decode was good enough for SMT2, then I bet 2x 4-Decode will be enough for SMT4.

 

[FlameTail]

Inverse SMT is the real deal.

 

[soresu]

Inverse SMT is the real deal.

SpecMT?

 

[Nothingness]

Inverse SMT is the real deal.

TMS. Job done.

 

[FlameTail]

I bet Zen6 desktop parts will be branded under Ryzen AI 400 series.

You guys think it will be called Ryzen 11000?

 

[Gideon]

I bet Zen6 desktop parts will be branded under Ryzen AI 400 series.

You guys think it will be called Ryzen 11000?

It definitely won't be 11000 series, but I also hope the "AI" naming silliness ends when the bubble bursts, before medusa.

Anyway back to topic:

I really do hope Zen 6 makes some sweeping changes to the cache hierarchy, as client and server parts will finally be totally separated (Desktop using same silicon as high-end laptops)

1MB L2 + large L3 certainly makes sense on server chips, but as Qualcomm and Apple seem to show, large shared L2 - up to 4 cores + MALL (Memory Attached Last Level Cache ) gives excellent results for client workloads. Though that's also with gargantuan L1 cache.(Intel's Lion Cove somewhat emulates it by renaming L1 to L0 and adding another 192KB layer as L1, but I doubt AMD will go down that route)

We have some hints for the direction AMD might choose. MI300C design has 64MB of MALL for each active-interposer chip (256MB in total) and Strix Halo, which has both 32MB of L3 per chiplet + 32MB of MALL on separate chiplet.

Given that , MALL is probably a given (possibly also in stacked form for V-cache chips) - it's just too important for mobile chips (power draw) and it won't hurt desktop either. But given the fact that Zen 6 will be the biggest packaging change for AMD since ... Zen 1 really (with Halo being the pipe-cleaner) I really do hope that the also reshuffle parts of the "uncore" on CCDs to take the most of the changes.

What do you guys think? Will AMD go down their usual conservative approach, Keeping the 48K L1D, 1MB L2 (per core) and 32MB L3 (shared in a 8 core CCX), or will they do something more bold?

IMO there is room for improvement. Strix Halo cache layout just seems ... kinda wasteful: (2x32MB of L3 , 32MB of MALL, 16 x 1MB of L2 = 112MB in total) with > 1MB of cache only accessable at ~ 10ns L3 latency with a per core cap of 32MB.

 

[Thibsie]

One has to try things first before being blunt and regret it.

 

[dr1337]

I feel like AMD is going to focus on enhancing branch prediction and OOE. 50% more ALUs and 33% more AGUs for only 20% more IPC, Z4 to Z5, sounds like an obvious bottleneck to me. They also ditched the dedicated branch unit and increased execution ports to 10 instead of 11, seems like low hanging fruit for a denser node.

I definitely expect less major changes to the core this time around, I'm fully convinced they're going to rework the IOD for Z6. RDNA4 and NPU for sure, I'd like them to include LLC but I think they might skip it because V-cache is still gonna be better.

 

[ryanjagtap]

I definitely expect less major changes to the core this time around, I'm fully convinced they're going to rework the IOD for Z6. RDNA4 and NPU for sure, I'd like them to include LLC but I think they might skip it because V-cache is still gonna be better.

Are you sure about the RDNA4 and NPU? The NPU will take a lot of space and 2CUs of RDNA2 is enough for basic display.
I think that the IOD will probably get a shrink to TSMC 4C, changes to the VCN for AV1 encode (presently only supports decode), faster memory support.
Anything else that could change?

 

[FlameTail]

Won't Medusa/Zen6 jump straight to RDNA5?

AMD Bald Eagle Point leaks as Zen 5 APU lineup with major cache upgrade

AMD could be preparing new laptop APUs to follow up the Zen 5-based Strix Point chips. Named “Bald Eagle Point”, the APUs also reportedly utilize Zen 5/5c cores like Strix Point alongside an RDNA 3.5 iGPU. However, the APUs apparently bring a major addition to the cache structure.

www.notebookcheck.net

The leaker also thinks that Bald Eagle Point is “likely to be cancelled” if Zen 6 Medusa is ready on time. However, Medusa’s launch is seemingly linked with RDNA 5 development. So, if RDNA 5 falls behind, AMD could release Bald Eagle Point as a minor refresh of Strix Point to hold the customers till Medusa comes out.

 

[yuri69]

2025 CES is most likely Strix Halo/Krakan
2025 Computex should be reserved for Strix Point refresh/Bald Eagle.

2026 is the earliest for Zen 6 since you know... 20+ months development cycle. RDNA 5 should be ready in 2026.

 

[FlameTail]

My guess;

If Medusa launches at 2026 CES,
Then no Bald Eagle Point.

If Medusa Launches at 2026 Computex,
Then Bald Eagle Point will be released in 2025 Computex or 2026 CES.

 

[gdansk]

2025 CES is most likely Strix Halo/Krakan
2025 Computex should be reserved for Strix Point refresh/Bald Eagle.

2026 is the earliest for Zen 6 since you know... 20+ months development cycle. RDNA 5 should be ready in 2026.

It is to be 2026. But I don't know why anyone is looking forward to Zen 6. Do people expect clock rates to increase?
The monolithic Zens so far don't look better at gaming or other latency-sensitive workloads than the X3D variants.

 

[dr1337]

I think it would be pretty weird for them to rework the IO die and not bring it up to modern specs. AMD isn't aggressive with NPU performance so I assume they're naturally optimizing for density.

Maybe RDNA5 has the right timing but I doubt it, AMD is generally slower to bring GPU architectures to APUs, we sat on vega for two years after RDNA had been a thing.

 

[Nothingness]

But I don't know why anyone is looking forward to Zen 6. Do people expect clock rates to increase?

I expect a better IPC. I have the feeling that with the new uarch, AMD has left some low hanging fruits to pick (due to time constraints, process, or strategy). Don't get me wrong, I think the Zen5 IPC improvement looks good on integer workloads, but with a new uarch there's always room for improvement in particular when a new process is invited to the party.

Is that enough to wait for Zen6? I'm unsure. But I'm eagerly waiting for desktop Zen5 benchmarks and deep technical reviews before making a decision.

 

[gdansk]

I think it would be pretty weird for them to rework the IO die and not bring it up to modern specs. AMD isn't aggressive with NPU performance so I assume they're naturally optimizing for density.

Maybe RDNA5 has the right timing but I doubt it, AMD is generally slower to bring GPU architectures to APUs, we sat on vega for two years after RDNA had been a thing.

APU has later RDNA revision than desktop right now.
Possible fluke or perhaps the future.

 

[CouncilorIrissa]

It is to be 2026. But I don't know why anyone is looking forward to Zen 6. Do people expect clock rates to increase?
The monolithic Zens so far don't look better at gaming or other latency-sensitive workloads than the X3D variants.

Not being limited by a single GMI3 link throughput will be nice. STX Halo is a preview in this respect.

 

[dr1337]

APU has later RDNA revision than desktop right now.
Possible fluke or perhaps the future.

Honestly that's part of my consideration but for another reason. AMD failed to deliver on RDNA3 having 50% more perf/watt, and as such thats why its been a year and a half and we haven't heard anything about RDNA4. I am assuming the reality is that RDNA progress has slowed and were getting closer to the time scales of original navi.

 

[FlameTail]

I expect a better IPC. I have the feeling that with the new uarch, AMD has left some low hanging fruits to pick (due to time constraints, process, or strategy). Don't get me wrong, I think the Zen5 IPC improvement looks good on integer workloads, but with a new uarch there's always room for improvement in particular when a new process is invited to the party.

Is that enough to wait for Zen6? I'm unsure. But I'm eagerly waiting for desktop Zen5 benchmarks and deep technical reviews before making a decision.

Could Zen6 bring greater than 20% IPC increase?

It's notable that although every Zen core has brought "double digit" IPC gains, it's never been >20%.

 

[gdansk]

Could Zen6 bring greater than 20% IPC increase?

It's notable that although every Zen core has brought "double digit" IPC gains, it's never been >20%.

It's around 10%.