Embarrassing for the two oldest CPU manufacturers to be gapped by them in such a fashion.
Embarrassing for the two oldest CPU manufacturers to be gapped by them in such a fashion.It's incredible that Apple and Arm are able to do IPC/Performance gains almost every year while Intel, AMD and QCOM are roughly on a 18 months cadence. And sometimes the latter 3 might not even bring a good performance uplift.
Would love that, but seriously, how do you do "enhanced INT" on the same multi use core?
If they put all the Zen6c cores as server cores and beeeg Zen6 cores for DT, different story, but...doesn't seem to be the goal yet.
Easy, bigger ROB, bigger INT PRF, moar schedulers, stuff like that.Out of curiosity what do people mean by enhanced INT performance? Enhanced memory sub-system performance? Better branch prediction? Different decode scheme?
Yeah it's more crazy talk. AMD client group would probably die. Zen 6 for *servers* in 2027? Might be the case. But there must be something for laptops before that.I have faith in the Zen team but the biggest issue is the cadence. It should be 16-18 months, over 24 months is crazy talk.
2024 Computex: Strix Point, Granite RidgeYeah it's more crazy talk. AMD client group would probably die. Zen 6 for *servers* in 2027? Might be the case. But there must be something for laptops before that.
So per your speculation AMD is to launch a desktop part that will score ~3900 GB6 1T in early 2027?2024 Computex: Strix Point, Granite Ridge
2025 CES: Kraken Point, Strix Halo
2025 Computex: Bald Eagle Point
2026 Computex: Medusa Point, Media Halo
2027 CES: Medusa Ridge
(Speculation)
Kepler L2 speculated that the reason for rb delay for 2027 was because desktop Zen6 used LPDDR6, and LPDDR6 LPCAMM modules won't be available until 2027....
The client revenue would indeed crater. STX will probably be the weakest 1T core by the end of 2024. Imagine how bad it will look in 2026, on a dated node, with atrocious C2C latency. That would mean forfeiting the entire laptop market.Yeah it's more crazy talk. AMD client group would probably die. Zen 6 for *servers* in 2027? Might be the case. But there must be something for laptops before that.
It's doable but what's the advantage? Cost more to make for a higher average all core clock? Not hopeful it allows 1T boost clocks to increase. And so I discount the possibility.Seems like the mood on various forums is a hope for N3* refresh in 25/26. No idea if that is even realistic if it wasn't planned for all along.
Seems like the mood on various forums is a hope for N3* refresh in 25/26. No idea if that is even realistic if it wasn't planned for all along.
if Medusa Ridge indeed uses LPDDR6-10667, it means 228 GB/s of bandwidth on a 192b bus!Kepler L2 speculated that the reason for rb delay for 2027 was because desktop Zen6 used LPDDR6, and LPDDR6 LPCAMM modules won't be available until 2027....
~5000.I think M6 would be available by that time and what do you reckon that would score?
What if, instead of a "refresh" that takes new development resources, it's the Zen5 that was originally intended and designed before being cut back due to falling back to N4P/X?I was one of those speculating for some kind of N3 "Zen 5+", but I really don't think its possible as that decision would've had to made some time ago.
Then AMD may as well go to AM6.Kepler L2 speculated that the reason for rb delay for 2027 was because desktop Zen6 used LPDDR6, and LPDDR6 LPCAMM modules won't be available until 2027....
Unless they manage to get significant IPC improvements the next couple of generations, ~5000 will only be possible at 5.5+ GHz.~5000.
On average, Apple aims for 10-15% ST increase with each generation.
M1: 2350
M2 : 2650
M3 : 3100
M4 : 3900
M5 :
M6 :
What if, instead of a "refresh" that takes new development resources, it's the Zen5 that was originally intended and designed before being cut back due to falling back to N4P/X?
It it is 2027 then N2 for even the client compute die becomes feasible.Zen 6 will still be bigger than Zen5. Moving to N3E/N3P on both the CCD and IOD. Improved memory controller and hopefully newer memory standards like LPCAMM. Not accounting for the minor core upgrades.
I have faith in the Zen team but the biggest issue is the cadence. It should be 16-18 months, over 24 months is crazy talk.
Wait for Strix Halo benchmarks first, especially in memory bound floating point apps.if Medusa Ridge indeed uses LPDDR6-10667, it means 228 GB/s of bandwidth on a 192b bus!
That's a huge bandwidth uplift, and could pave the way for 24 core or even 32 core Zen6 desktop parts.
You know there was a rumour of ARL-R with 8P+32E? That supposedly got cancelled because there was not enough memory bandwidth to feed that beast with DDR5.
Apple M4 (4.4 GHz) already enough IPC, and if you were to overclock it (hypothetically) to 5.5 GHz+, you would approach ~5000 points.Unless they manage to get significant IPC improvements the next couple of generations, ~5000 will only be possible at 5.5+ GHz.
Remember IPC improvements were practically zero from M1->M3, only M4 shows a medium IPC increase of ~7%.
~5000.
On average, Apple aims for 10-15% ST increase with each generation.
M1: 2350
M2 : 2650
M3 : 3100
M4 : 3900
M5 :
M6 :
I mean it probably could power a spaceship provided it has enough ram. /sM5 is the multitronic system, with such good AI it is capable of running a starship by itself. So it may have a bigger performance jump that previous generations - and will kill anyone who tries to turn it off (or report unsatisfying benchmark results)
Remarkable how the mood has shifted so seismically.Seems like the mood on various forums is a hope for N3* refresh in 25/26. No idea if that is even realistic if it wasn't planned for all along.
I mean it probably could power a spaceship provided it has enough ram. /s