Would love to be a little mouse to climb into Kepler's head and see how he came to that >40% conclusion.Remarkable how the mood has shifted so seismically.
Why, only a few months ago we were talking about how Zen5's 40% 1T improvement would make it the undisputed leader of ST performance, totally annihilating the competition and put AMD in the lead for years to come!
They "extrapolated" 32% 1t gains from Turin 96C being 50% faster than Genoa 96C in SPECint rate N at +25% power.Would love to be a little mouse to climb into Kepler's head and see how he came to that >40% conclusion.
Apparently AMD lied bold faced. Which if true, is very concerning after RDNA 3. The amount of straight up lies is making things difficult with them.
Remarkable how the mood has shifted so seismically.
Why, only a few months ago we were talking about how Zen5's 40% 1T improvement would make it the undisputed leader of ST performance, totally annihilating the competition and put AMD in the lead for years to come!
Nah. FlameTail is making sure the hype train continues there 🤭Well, looks a lot like the mood in the Qualcomm thread, huh ?
This would make a good steam deck 2, I guessIt would seem straightforward to either stick with monolithic like Strix Point and move to N3e. On N3e, they can finflex the P cores and the C cores appropriately and also add on the speculated MALL cache. With the MALL cache at 16-32 MB, a single speed bin increase on the LPDDR5X ram could support 20CU of RDNA3.5 quite well. That's just two additional WGPs. The next Kraken could grow to 12CU and keep the same core arrangement, but double the L3 in the ccx.
Delaying for actual manufactured memory is not necessary as long as the standard spec is published and the IO of the SoC follows that spec.Kepler L2 speculated that the reason for rb delay for 2027 was because desktop Zen6 used LPDDR6, and LPDDR6 LPCAMM modules won't be available until 2027....
I'm seriously hoping that the hi end desktop (non TR) platform goes up to 32C.What is the latest on zen 6 ?
16x p core ccd with 3d v cache ??
Or
8x p core ccd with 3dv cache + 16x c core spam ??
& now that AMD has started releasing laptop APUs first, will they optimize p-core for client & c-core for servers ???
It's not about what is important in terms of AMD's own goals, it's about what competitors offer and whether AMD can offer the same or better.I'd love more than 16 cores but I seriously don't think its very important on desktop in the next ~3-4 years (Z5 and Z6). Though, if there is very little IPC gain (which has made up for more cores in lots of MT apps since Z2) I might change my mind.
He always could've been mislead by his sources.Would love to be a little mouse to climb into Kepler's head and see how he came to that >40% conclusion.
Apparently AMD lied bold faced. Which if true, is very concerning after RDNA 3. The amount of straight up lies is making things difficult with them.
His source is AMD, so...yes?He always could've been mislead by his sources.
Probably an engineering partner for AMDHis source is AMD, so...yes?
Its wouldn't be unexpected at all for it to support LPDDR6 only. LPDDR6 is quite unique, and supporting LPDDR5X or DDR6 from the same memory controller is going to be a pain.Unless LPDDR6 is literally the only standard it supports, which would be insane for AMD to do for a brand new stankard
It wouldn't be the first time AMD had supported more than one standard from the same controller.and supporting LPDDR5X or DDR6 from the same memory controller is going to be a pain
It wouldn't be the first time AMD had supported more than one standard from the same controller.
IIRC Deneb/Phenom II supported both DDR2 and DDR3.
I feel some people really don’t understand what market segments are. Apple has a big die that costs a ton of money to make. Due to the fact they focus on premium devices AND the fact they profit off the entire system, they can afford to pay more. AMD has to design their chips to scale from under $200 and up, and they only make money off the CPU itself (user is not guaranteed to buy other components). Therefore they use smaller, high frequency dies. They also have to deal with the fact that users still think that “more ghz is better”.That’s because current AMD designs rely on high frequencies. I want to see AMD design a M1 clone for Zen. Big L2 cache and low frequency and high IPC, it would sell so much. It would make the Steam Deck so good. I wonder if such a design is possible with x86. Cause you have to remember ARM/Apple cores are also much wider than x86.
Apart from the Max die(which I agree AMD cannot do for client or can it? Strix Halo...) the M Pro and base M chips are not big at all.I feel some people really don’t understand what market segments are. Apple has a big die that costs a ton of money to make.
AMDs GPU game seems to be to make all of the units as small as possible and at some point leverage that and their ciplet tech to makes GPU that is bigger than what Nvidia can provide. Whether that happens or not...they seem to get cancelledI feel some people really don’t understand what market segments are. Apple has a big die that costs a ton of money to make. Due to the fact they focus on premium devices AND the fact they profit off the entire system, they can afford to pay more. AMD has to design their chips to scale from under $200 and up, and they only make money off the CPU itself (user is not guaranteed to buy other components). Therefore they use smaller, high frequency dies. They also have to deal with the fact that users still think that “more ghz is better”.
AMD knows where the optimum balance is for PC users and I think they’ve got it right.
Note that they also want to do this with their GPUs to an extent.