Superscalar means "can execute more than one operation at the same time", and OoO means "can execute operations out of strict program order".
oh I was way off. I thought it meant high IPC with low clocks. Apologies.
So far the core design used in desktop aside for monolith APUs has been designed for servers. For Zen 6 it seems desktop may get cores designed for mobile instead even for chiplet MCM chips.Going back on track, I hope the rumours about AMD separating core designs for each segment are true for Zen6.
At least now we know to dismiss any claims of <10% IPC gains for Zen 6, with prejudice. If AMD delivers more, good for them and we can consider it a bonus but keeping our expectations to <=10% IPC will ensure that we don't get disappointed or burn unnecessary energy fantasizing about benchmark scores we'll never get to see upon product launch.Expecting sensible discourse from a new µArch thread 16+ months out from release is a fools errand.
Just watch and enjoy the crazy train 😂
Th slides didn't say anything about clock speeds.At least now we know to dismiss any claims of <10% IPC gains for Zen 6, with prejudice. If AMD delivers more, good for them and we can consider it a bonus but keeping our expectations to <=10% IPC will ensure that we don't get disappointed or burn unnecessary energy fantasizing about benchmark scores we'll never get to see upon product launch.
Very interesting. But what's the difference between Granite Ridge CCDs and Strix Halo CCDs? Would they be meaningfully superior so as to warrant making a Zen5+ generation out of it?Just a wild guess: If Zen 5 CCD from Strix Halo (5nm?) , and Zen 6 CCD from Medusa Halo (3nm?), and Zen 6 CCD from Medusa Ridge (3nm?), are interchangable within the same IO die (like Zen 2/3 and 4/5 on desktop were), There's a chance that AMD can make "Zen5+" of sorts, on desktop: Take the IO die from Zen6 Medusa Ridge, and attach Zen 5 Strix Halo CCD to it. No new parts required, just reusing existing ones. Would be like a cheap version of Zen 6, since it wouldn't use 3nm Zen 6 CCDs.
all of this is just a made up thing in my head, based on absolutely nothing.
No difference, just a new IO die with (potentially) higher memory throuput and lower latency.Very interesting. But what's the difference between Granite Ridge CCDs and Strix Halo CCDs? Would they be meaningfully superior so as to warrant making a Zen5+ generation out of it?
It uses USR PHYs between the IOD and CCD, similar tech as RDNA3, several times more interconnect bandwidth and lower latency.No difference, just a new IO die with (potentially) higher memory speed support and lower memory latency.
Chasing frequency helped Intel a lot, didn't it?Let the Zen6 = 6.6 GHz hype train begin!
The only problem is, AMD always picks the dirt cheap solution. I still refuse to believe they will use something really advanced for cheapo CPU (e.g. 6c $280 SKUs).Strix Halo is a preview of Zen 6 platform improvements, and it kinda has to show major gains across some apps vs GNR or AMD is in a real pickle.
InFO is very cheap, been used in phones for eons.use something really advanced
According to who?Zen 6 is looking like early 2027 right now.
But that was a good news whereas this would be a bad news. You know how it goes...According to who?
The same people who told you Zen 5 would be a Conroe moment.
IIRC out of order is why CPUs need a branch predictor?Superscalar means "can execute more than one operation at the same time", and OoO means "can execute operations out of strict program order".
Silly notion.The same people who told you Zen 5 would be a Conroe moment.
From the dual decoders in Zen 5 and the triple decoders in Skymont they already are.Engineers/architects need to get more creative.
I'm less interested in silly clock frequencies they can manage in 1 -> a few cores as more reasonable frequencies they can manage very efficiently at dozens of cores together under load.Let the Zen6 = 6.6 GHz hype train begin!
X86 decoding is much harder than decoding on ARM, I suppose.why can’t AMD/Intel design a 10-wide decoder instead of these 2x4 and 3x3 ones?
x86 decoding costs kinda explode when you go bigger.why can’t AMD/Intel design a 10-wide decoder instead of these 2x4 and 3x3 ones?
Intel does have a 6-wide decoder in Golden Cove and 8-wide in Lion Cove.why can’t AMD/Intel design a 10-wide decoder instead of these 2x4 and 3x3 ones?
My guess would be changing design strategies to compete with ARM server SoC core-a-palooza.why can’t AMD/Intel design a 10-wide decoder instead of these 2x4 and 3x3 ones?
Oh it's not amd64-only, it just throws the legacy init bits out.I wonder if shifting to the x64 only "X86-S" spec will make it easier to design wider decoders without splitting them up to several narrower ones.
It doesn't look like it. But it should reduce the amount of required tests a bit.I wonder if shifting to the x64 only "X86-S" spec will make it easier to design wider decoders without splitting them up to several narrower ones.