Question Zen 6 Speculation Thread

[DavidC1]

And still x64 decoding takes longer so they add more decoding pipeline stages to break the work into multiple steps and add micro-op cache to reduce the energy cost associated with repeatedly decoding the same instructions into micro-ops. Some ARM designs have a micro-op cache but apparently not the fastest ones.

They claim it's energy reduction, but I think that's a side effect of the real goal: Higher clocks.

Conroe: 14 stages
Nehalem: 16 stages(due to Turbo)
Sandy Bridge: 14-18. 14 on a hit, 18 on a miss. Uop cache itself adds extra 2 stages, and 2 stages more on a miss. SNB had even better Turbo.

So they are trying to get 18 stage clocks with 14 stage performance. Remember the root of the uop cache idea is Trace Cache. Willamette and Northwood had 1 decoder and relied almost entirely on TC for decode. So performance is not just about averages but reducing worst-case scenarios and missing TC would mean 1-wide decode.

 

[MadRat]

If you running 16-bit operation would it be best run in a 16-bit off-chip co-processor. Likewise, run simpler 32-bit operations in a 32-bit off-chip co-processor. Locate the co-processors on the external cache chips. Isolate x86-64 and only the complex 32-bit procedures to the main core. You literally can design 16-bit legacy systems on a chip for backwards compatibility. So what if co-processors are locked in step with memory timing. Its still 2500x faster than the original CPU cores.

 

[Wolverine2349]

Silly notion.

Obviously Zen1 is AMD's Conroe moment as it's predecessors based on Bulldozer were their Pentium 4.

To call Zen5 their Conroe moment is to imply that Zen1-4 was a dumpster fire period of µArch design which is manifestly untrue.

Zen1 was kind of a conroe moment for AMD but not in terms of knocking intel. AMD was so far behind that Zen 1 lessoned the gap with intel but still behind especially regarding latency.

Prior to Conroe, intel had netburst though despite much worse ipc than Athlon64, it clocked much higher and closed gap some though still behind Athlon64.

Once intel released Conroe, it blew Athlon 64 out snd had an even bigger UPC increase over Netburst like almost double like 100% than Zen 1 over Pile Diver which was only 50 percent.

Still impressive none the less but Intel since Conroe really blew out AMD until AMD released Zen 2 in which it got even.

 

[soresu]

Still impressive none the less but Intel since Conroe really blew out AMD until AMD released Zen 2 in which it got even.

Process node leadership is playing a part here which you have overlooked.

The fact that K8 was trouncing NetBurst despite K8 being on an inferior node actually makes it worse.

Also Zen2 only got even in desktop and mobile, in servers (and TR enthusiast desktop) through chiplet scaling it crushed Intel, in some significant part due again to TSMC passing Intel in their self imposed 10nm quick sand.

 

[Wolverine2349]

Process node leadership is playing a part here which you have overlooked.

The fact that K8 was trouncing NetBurst despite K8 being on an inferior node actually makes it worse.

Also Zen2 only got even in desktop and mobile, in servers (and TR enthusiast desktop) through chiplet scaling it crushed Intel, in some significant part due again to TSMC passing Intel in their self imposed 10nm quick sand.

Was K8 an inferior node? I remember it was on 90nm and so was Pentium 4. Weren't they the same. Eventually Pentium D Pressler went to 65nm so a better node??

 

[soresu]

Was K8 an inferior node? I remember it was on 90nm and so was Pentium 4. Weren't they the same. Eventually Pentium D Pressler went to 65nm so a better node??

Ah, it seems I Mandela'd Intel's lead time as being significantly longer.

They had 8 months lead for 90nm, and 11-12 months for 65nm, though IIRC AMD 65nm wasn't that impressive.

 

[igor_kavinski]

though IIRC AMD 65nm wasn't that impressive.

I remember AMD touted their 65nm SOI process as something really revolutionary. They (or maybe GloFlo) kept using SOI for a really long time. Never understood their obsession with it.

 

[soresu]

I remember AMD touted their 65nm SOI process as something really revolutionary. They (or maybe GloFlo) kept using SOI for a really long time. Never understood their obsession with it.

Perhaps I should clarify, I don't remember the difference from their 90nm -> 65nm parts being that impressive.

 

[Tuna-Fish]

Was K8 an inferior node? I remember it was on 90nm and so was Pentium 4. Weren't they the same. Eventually Pentium D Pressler went to 65nm so a better node??

Ah, it seems I Mandela'd Intel's lead time as being significantly longer.

They had 8 months lead for 90nm, and 11-12 months for 65nm, though IIRC AMD 65nm wasn't that impressive.

I remember AMD touted their 65nm SOI process as something really revolutionary. They (or maybe GloFlo) kept using SOI for a really long time. Never understood their obsession with it.

AMD's 90nm SOI node was significantly better than Intel's 90nm bulk. Intel started having serious scaling issues because of quantum tunneling on their 90nm node, at which point AMD was really triumphant about how their SOI node was protecting them from the same issues and just generally better. AMD hit the same issues on their 65nm node, which is what caused both the delay and the anemic performance.

IIRC it was even worse than it sounds, because AMD upgraded their fabs in place, so they took a fab offline to convert to 65nm just as the demand for Opteron would have been at its peak, and then the upgrade lasted much longer than it should have.

 

[DisEnchantment]

Somewhere in 2025-26 is AMD's plan for Z6 and OpenSIL.

 

[Gideon]

Yeah it seems they eventually plan to remove AGESA entirelly. Great!

AMD Reveals Latest Plans For Open-Source openSIL With Replacing AGESA, Zen 6 Milestone - Phoronix

www.phoronix.com

 

[Tuna-Fish]

Somewhere in 2025-26 is AMD's plan for Z6 and OpenSIL.

This implies that Zen6 is on AM5. No flavor of DDR6 will be ready for mass adoption at that point.

 

[marees]

This implies that Zen6 is on AM5. No flavor of DDR6 will be ready for mass adoption at that point.

Probably desktop z6 is on am5

But server could support ddr6 ?

 

[Tuna-Fish]

Probably desktop z6 is on am5

But server could support ddr6 ?

AMD would be unable to sell CPUs because the server vendors would not be able to procure ram for them. The DDR6 1.0 spec is not expected until Q2 next year. The fastest time from spec to sufficient availability for mass adoption was iirc 17 months. That's basically 2027.

 

[DisEnchantment]

It seems likely that next gen server will be DDR5 based MRDIMMs. DT/Client unsure, could be LPDDR6 CAMM2.

 

[yuri69]

View attachment 106887

Somewhere in 2025-26 is AMD's plan for Z6 and OpenSIL.

If I'm reading this correctly the openSIL release is stated to be 1Q after Venice launch. The release "green star mark" is located at end of 2026. So Q3 2026 sounds about right for Venice.

 

[Hitman928]

If I'm reading this correctly the openSIL release is stated to be 1Q after Venice launch. The release "green star mark" is located at end of 2026. So Q3 2026 sounds about right for Venice.

Obviously AMD’s roadmap is wrong, because I have it on very good authority (internet leakers) that we won’t see Zen 6 at all until 2027.

 

[Mopetar]

Obviously AMD’s roadmap is wrong, because I have it on very good authority (internet leakers) that we won’t see Zen 6 at all until 2027.

In before MLID scoops up your post for his next video.

 

[APU_Fusion]

I predict +40% ipc over zen 5 give or take 40% to 60% either way

 

[Bigos]

I predict your prediction is way off.

 

[gdansk]

I predict your prediction is way off.

It's such a wide range it seems hard to be wrong. -20% to 100% is probably right.

 

[MadRat]

DDR6 will probably appear on APU chips to maintain AM5 compatibility. Literally necessary to compete with Apple for media processing.

 

[Anhiel]

I doubt that. There's no reason for AMD to invest support in that generation so soon even if they are working on DDR6 support now. Mind you even before AM5 I was saying the change to PCIe 6 and 7 would come within years so I certainly would welcome it.

The best to hope for is the introduction or support of CXL memory modules. I hope that would give rise later to a combination of both replaceable memory modules and on package memory. Other than low end mobiles consumers shouldn't accept on package memory only.

 

[igor_kavinski]

Someone needs to do some membw intensive test with pegged Zen 5 cores (thus excluding the Zen5c ones) on the HX 370 with LPDDR5-8533 and compare that with desktop 9700X stock RAM score with same amount of cores to see if Zen 5 is bw starved in the desktop version.

 

[MadRat]

I doubt that. There's no reason for AMD to invest support in that generation so soon even if they are working on DDR6 support now. Mind you even before AM5 I was saying the change to PCIe 6 and 7 would come within years so I certainly would welcome it.

AMD could support DDR6 immediately. AMD burned in support for external memory controllers. An external memory controller can literally be whatever they define. That is the beauty of supporting an external memory controller. What they aim for is profit. Can they profit from the product? Probably not atm.