Question Zen 6 Speculation Thread

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Mahboi

Golden Member
Apr 4, 2024
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Anybody care to brief me about what makes FD-SOI nonsense?
Looks very interesting on paper, I fail to see why that would be nonsense. Costs?
 

Mahboi

Golden Member
Apr 4, 2024
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Because like beta max it lost......
that helped a lot, especially since I have no idea what betamax is

"Betamax is a consumer-level analog recording and cassette format of magnetic tape for video, commonly known as a video cassette recorder. It was developed by Sony and was released in Japan on

May 10, 1975,"​


Yeah no shock I have no idea what that is
 

marees

Senior member
Apr 28, 2024
371
427
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that helped a lot, especially since I have no idea what betamax is

"Betamax is a consumer-level analog recording and cassette format of magnetic tape for video, commonly known as a video cassette recorder. It was developed by Sony and was released in Japan on

May 10, 1975,"​


Yeah no shock I have no idea what that is
Sony developed multiple standards of their own. Some clicked. Some didn’t

Betamax lost to VHS (video tape formats)
Bluray won vs HD-DVD
Their memory card format lost to SD

I believe Samsung have their own HDR format
& then there is Dolby Atmos vs some other format

There was nothing wrong with any of the above formats. Some won & some lost
 
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itsmydamnation

Platinum Member
Feb 6, 2011
2,911
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that helped a lot, especially since I have no idea what betamax is

"Betamax is a consumer-level analog recording and cassette format of magnetic tape for video, commonly known as a video cassette recorder. It was developed by Sony and was released in Japan on

May 10, 1975,"​


Yeah no shock I have no idea what that is
ok then , like Windows Phone 7, it lost , does that help ?
 
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DrMrLordX

Lifer
Apr 27, 2000
22,000
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@Mahboi

All joke posts aside, SOI (Silicon on Insulator) lost out to FinFETs some time ago. It hasn't really been a contest in about a decade. Samsung allegedly has (or had) some FD-SOI tech and GF still produces FD-SOI, but that's about it. It certainly isn't used in anything cutting edge.

I don't know why we're discussing it in a Zen6 thread. AMD will not be using SOI nodes in the future.
 
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marees

Senior member
Apr 28, 2024
371
427
96
@Mahboi

All joke posts aside, SOI (Silicon on Insulator) lost out to FinFETs some time ago. It hasn't really been a contest in about a decade. Samsung allegedly has (or had) some FD-SOI tech and GF still produces FD-SOI, but that's about it. It certainly isn't used in anything cutting edge.

I don't know why we're discussing it in a Zen6 thread. AMD will not be using SOI nodes in the future.
The last I saw, global foundries was the only one pushing SOI. Neither Intel nor TSMC does it.

GF was touting that radio modems can be done in SOI(or was it FINFET)? If so maybe mediatek / qualcomm / huaweii can look at it
 

marees

Senior member
Apr 28, 2024
371
427
96
The last I saw, global foundries was the only one pushing SOI. Neither Intel nor TSMC does it.

GF was touting that radio modems can be done in SOI(or was it FINFET)? If so maybe mediatek / qualcomm / huaweii can look at it
4 years ago:

Bami Bastani, senior vice president of general manager of the mobile and wireless business unit at Globalfoundries said: “The 12FDX program is alive and well. It has a lot in common with our 12nm FinFET process so we are about 60 percent done. We are optimizing the process.” Bastani added that Globalfoundries expects to be in production on 12FDX in 2023 or 2024.




From 9 years ago:


As per GF
FD-SOI is really a technology optimized for the low-cost IoT, battery-powered, low-end mobile and automotive applications.
 

NostaSeronx

Diamond Member
Sep 18, 2011
3,705
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I don't know why we're discussing it in a Zen6 thread. AMD will not be using SOI nodes in the future.
Low-power core options by themselves move to the best PPAC node. Thus, Zen6 Low-power core option in a SoC/APU by themselves without Zen6 Classic/Compact. Would naturally drift to the foundry that has the overall best cost-to-performance/power ratio.

Entry (Duron (Spitfire) -> A9-series (Stoney)) = 40% of the market
Mainstream (Llano -> Trinity -> Kaveri -> Bristol -> Dali/Raven2/Pollock -> Mendocino -> Sonoma) = 20% of the market
Premium/Performance (Raven/Renoir/Cezanne/Phoenix/Strix) = 40% of the market

First mention of something Bobcat = November 2006
First mention of Bobcat being cancelled = September 2008
~~ Bobcat went through re-iteration three times ~~
Rather than launching in 2008, the design launched in January 2011.

Clustered Microarchitecture at AMD is even longer:
1997-2004 for first iteration.
2005-2007 for second iteration.
2008-2011 for third iteration.
Then, re-introduction of clustered IP for the clustered FPU Zen3/Zen4/Zen5/Zen6.
As well, re-introduction of clustered IP for the clustered FE Zen5/Zen6.

Zen6LP cores w/o other Zen6/Zen6c cores will naturally only be on 12FDX. Think, instead of 2x4-wide, it is 2x2-wide and 1 ALU/MUL+1 ALU/BR *2 with even smaller FP128 w/ only VEX-encoded instructions. Allowing for high Fmax in a ultra-low-power profile. Since, the low power core is generally always smaller than their high performance counterparts. Alastor 4-wide vs Ascalon 8-wide for example.
<-- this effect is more pronounced in FDSOI than in FF/Bulk.
 
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marees

Senior member
Apr 28, 2024
371
427
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Low-power core options by themselves move to the best PPAC node. Thus, Zen6 Low-power core option in a SoC/APU by themselves without Zen6 Classic/Compact. Would naturally drift to the foundry that has the overall best cost-to-performance/power ratio.
View attachment 107596
Entry (Duron (Spitfire) -> A9-series (Stoney)) = 40% of the market
Mainstream (Llano -> Trinity -> Kaveri -> Bristol -> Dali/Raven2/Pollock -> Mendocino -> Sonoma) = 20% of the market
Premium/Performance (Raven/Renoir/Cezanne/Phoenix/Strix) = 40% of the market

First mention of something Bobcat = November 2006
First mention of Bobcat being cancelled = September 2008
~~ Bobcat went through re-iteration three times ~~
Rather than launching in 2008, the design launched in January 2011.

Clustered Microarchitecture at AMD is even longer:
1997-2004 for first iteration.
2005-2007 for second iteration.
2008-2011 for third iteration.
Then, re-introduction of clustered IP for the clustered FPU Zen3/Zen4/Zen5/Zen6.
As well, re-introduction of clustered IP for the clustered FE Zen5/Zen6.

Zen6LP cores w/o other Zen6/Zen6c cores will naturally only be on 12FDX. Think, instead of 2x4-wide, it is 2x2-wide and 1 ALU/MUL+1 ALU/BR *2 with even smaller FP128 w/ only VEX-encoded instructions. Allowing for high Fmax in a ultra-low-power profile. Since, the low power core is generally always smaller than their high performance counterparts. Alastor 4-wide vs Ascalon 8-wide for example.
View attachment 107604 <-- this effect is more pronounced in FDSOI than in FF/Bulk.
That was very confusing.

Did AMD use FD-SOI ever ?

The PS4 bobcat/jaguar were on TSMC

 
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NostaSeronx

Diamond Member
Sep 18, 2011
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That was very confusing.

Did AMD use FD-SOI ever ?

The PS4 bobcat/jaguar were on TSMC

AMD's GF28A was originally 28nm FDSOI Gen2. Bhavani/Beema/Carrizo are GF28A products. Thus were at one time FDSOI at one point.

28LPS -> 28SLP -> 28HPP, 28SHP isn't shown but it only had a 5% increase in performance relative to 28HPP.

Jha = Scaling (14XM/14LPP -> 10XM/10LP -> 7LP -> 5nm/3nm GAA, etc), so FDSOI kept getting kicked to the curb.
Cau = Re-directioning FDSOI to leading edge "More than Moore", where FDSOI because of TI gets to do this:
 
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NostaSeronx

Diamond Member
Sep 18, 2011
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Give it up Seronx, they're not using FD-SOI
Between 16nm and 7nm is the 12FDX Versal set for 2026. Simplifying and producing a cost-optimized solution replacing R2314+VE2302 with a single package solution. The main core on the x86-64 side is the Zen6LP core.

They are going to use FDSOI/FDX. XQRKU060 successor is at 12FDX. Tesla has to patch 130K cars because their Ryzen APUs are overheating. => Another 12FDX processor. Auto-Select processors are Zen only, Auto-Premium processors are Zen+Versal.
<-- track selection shared between 22FDX/22FDX+/12FDX. "For the automotive industry, GF announced 22FDX+ AutoPro™ 150. This offering extends the capabilities of 22FDX+ for use in automotive up to 150°C with corner tightened standard cell libraries and optimized SRAM compilers to boost chip performance by 10% or reduce power consumption by up to 20%. Novel SRAM bitcells and compilers that are optimized with reverse body-biasing, a capability only possible in FDSOI technology, can deliver up to 60% leakage reduction at 150°C junction temperature." This should be carried over to 12FDX for its AG0/150c. Since, the 22FDX~12FDX platform shares the >175c Tj with another FDSOI project.

$25k EV ~~ 12FDX / Zen6LP
Battery Type A = 15 to 35C operating temperature
Battery Type B = -70 to 130C operating temperature <-- requires less cooling complexity, overall cheaper to manufacture. Kills cooling on the Infotainment+Versal SoCs.
 
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LightningZ71

Golden Member
Mar 10, 2017
1,783
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The main issue, as I see it, is that GF has always been at least 2 years behind where they need to be with their fdsoi development as compared to economical legacy nodes. Compound that with a notably different PDK and even if it was cheaper per chip on a variable cost basis, ammortizing the fixed costs will always likely make it uncompetitive.

AMD likely does their due dilligence and continues to examine their options, but, it should never go farther than that.

FDSOI, assuming it scales down to sub "5nm" levels, MAY offer surperior SRAM scaling as compared to FinFet and Gaa approaches. But it remains to be seen if it is economical. We COULD, one day, MAYBE see 3d cache dies made with FDSOI, but I don't really see it anytime soon.
 
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soresu

Diamond Member
Dec 19, 2014
3,190
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Seems like other than something radical like MRAM that we might see SRAM go 3D multilayer like is also in DRAMs capacitorless future in order to maintain scaling.

Obviously right now it's not particularly viable for on die cache, but once inter die stacking contacts go upwards into the count of millions it's definitely possible that we could see L3 or even L2 go off die to some specialised 3D SRAM process.
 
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