Question Zen 6 Speculation Thread

[Fjodor2001]

On a serious note though in a lot of workloads Zen 5 is going to be memory bandwidth bound. Zen 4 already is in some of the most rigourous workloads, and even in some games etc you can see benefits to more memory bandwidth (see: launch day Starfield).

Even just based off of information in the public domain Zen 5 is a much bigger core but likely to be a very similar memory setup. Bandwidth bottlenecks are practically ensured. Even if Zen 6 were to switch to a new platform with much more robust I/O, it seems unlikely it would provide enough bandwidth to feed 40 cores, even if 8+32. That's over double the existing core count. Even if you want to break them down by clocks and assume 8 Zen 6 cores running at 4.5GHz and 32 Zen 6 cores running at 3.2GHz (which are likely conservative values for both), that's still going to need vastly more memory bandwidth than the current 16 cores running at ~5GHz (which is likely an overestimate if anything).

It varies per MT workload if it's memory bandwidth bound or not.

Also, there will be uncore and memory controller improvements, DDR5 speed bumps, etc coming with Zen6 / ArrowLakeRefresh.

 

[adroc_thurston]

?

Fun stuff.

Some say 2025/2026. And Zen6 and ArrowLakeRefresh is when?

Wojakspamming kid posted JEDEC slideware on twitter. please.

Clarification and proof needed, for why you think CPU perf cannot be improved beyond Zen5 16C without DDR6.

I've told you whom to ask.

Link?

Don't beg.

DIY is not representative of DT market share.

DT isn't a relevant market either.

No, generally. AMD will lose MT crown to Intel on DT?

Cinememe it is.

Well, then I'll repeat:

"for those looking for max MT perf on DT, at lowest cost, and highest perf/W, Intel will be the best option from ArrowLakeRefresh / Zen6 onwards?"

Yes/No? And why?

Begging again. Bad.

So you have no source, meaning your claim is moot.

Don't beg. Fight for it. Get it by your hands.

 

[Mahboi]

On a serious note though in a lot of workloads Zen 5 is going to be memory bandwidth bound. Zen 4 already is in some of the most rigourous workloads, and even in some games etc you can see benefits to more memory bandwidth (see: launch day Starfield).

Even just based off of information in the public domain Zen 5 is a much bigger core but likely to be a very similar memory setup. Bandwidth bottlenecks are practically ensured. Even if Zen 6 were to switch to a new platform with much more robust I/O, it seems unlikely it would provide enough bandwidth to feed 40 cores, even if 8+32. That's over double the existing core count. Even if you want to break them down by clocks and assume 8 Zen 6 cores running at 4.5GHz and 32 Zen 6 cores running at 3.2GHz (which are likely conservative values for both), that's still going to need vastly more memory bandwidth than the current 16 cores running at ~5GHz (which is likely an overestimate if anything).

Every day, Jensen's power grows.

 

[Fjodor2001]

Fun stuff.

?

Wojakspamming kid posted JEDEC slideware on twitter. please.

Cool kid. Any official source?

I've told you whom to ask.

No.

Don't beg.

Don't claim things you cannot back up with reliable sources.

DT isn't a relevant market either.

It's what matters. DYI is only a subsection of DT, so matters less.

Cinememe it is.

So again, AMD will lose MT crown to Intel?

Begging again. Bad.

Don't claim things you cannot back up with reliable sources. Again.

Don't beg. Fight for it. Get it by your hands.

Don't claim things you cannot back up with reliable sources. Again.

 

[adroc_thurston]

Any official source?

JEDEC IS THE OFFICIAL SOURCE, THEY WRITE THE GODDAMN SPEC.
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa

It's what matters. DYI is only a subsection of DT, so matters less.

non-DIY DT is quad-core poorboxes for office slaves.

Don't claim things you cannot back up with reliable sources. Again.

Silly beggar.

 

[chotutpisat]

Silly beggar.

How is asking for a source begging when you are the one making claims? Its simply high ego shitty behavior that doesn't contribute anything to the conversation.

 

[StefanR5R]

AMD will lose MT crown to Intel?

When MT workloads aren't memory bandwidth bound, they are power bound. Intel have a lot of catching up to do in perf/power in order to catch up in MT performance.

 

[uzzi38]

It varies per MT workload if it's memory bandwidth bound or not.

Also, there will be uncore and memory controller improvements, DDR5 speed bumps, etc coming with Zen6 / ArrowLakeRefresh.

Aside from stuff like Cinebench R23 and older (Cinebench 24 is also memory bandwidth bound) most MT workloads are not light on memory bandwidth usage.

Those littles would contribute to very little. I could maybe see a potential future with LPDDR6 on MSDT where 8+16 becomes a reasonable option, but not 8+32.

 

[uzzi38]

So provide source?

For comparison, just as an example, this says 2024/2025:

DDR6 RAM: The next-gen memory standard, explained

Unsurprisingly, DDR6 memory will gradually replace the current DDR5 memory over the next few years, but what do we actually know about the upcoming memory standard? We'll tell you.

www.pcworld.com

And this says 2025:

DDR6 looks set to double data speeds over DDR5, with DDR6-21000 being the ultimate target

Development is still ongoing so don't expect to see it any time soon, though.

www.pcgamer.com

Gaming peasants do not need more than 8 (or max 16) cores from your previous claims. Or have you changed your mind?

Have you been in an office that is working with performance DT PCs? If not, I assume they were using laptops instead, do DT would be moot anyway.

If the standard is expected to be finalized in 2024-2025 as stated there it's extremely unlikely to expect any real volume until 2026 at earliest. Honestly H2 26 for actual platforms supporting it is a very reasonable take.

 

[uzzi38]

Agreed. Hence the expected 8P+32E cores.

That's just a waste of money then, you're getting severe diminishing returns by adding more cores within the same restricted power budget. A SKU like that is much like the 3990X on TRX4, functionally only useful to a very small handful of people who's workloads can actually cope with the poor memory bandwidth and prohibitively expensive to those that only see modest scaling from more sensible options.

 

[marees]

and highest perf/W, Intel will be the best option

When was the last time Intel won something on perf/watt ?

 

[StefanR5R]

Hence the expected 8P+32E cores.

Though the currently available E cores are AE cores, not PE cores.

 

[Fjodor2001]

When was the last time Intel won something on perf/watt ?

Agreed. A long time ago! 🤣

But that was not the point. Point was perf/watt regardless of whether AMD or Intel (or perhaps even some other CPU manufacturer). Hence E-cores, ZenC, ZenLP and what not, and a lot of them.

 

[Fjodor2001]

Aside from stuff like Cinebench R23 and older (Cinebench 24 is also memory bandwidth bound) most MT workloads are not light on memory bandwidth usage.

Based on what can such a general conclusion be drawn?

What about e.g. video transcoding, source code compilation, etc. Very MT heavy. But not really a lot of memory bandwidth needed for that.

 

[Markfw]

We're talking about timelines for DDR6 availability, not specs.

No, low core count DT is for gaming peasants. High core count DT is for performance users / office workers.

And anyway, DT market segment includes all of the DT categories (gaming /office / low-perf / SFF/ ...). DYI is only a subsection of DT. Intel has the biggest DT market share, whether we like it or not. And they are gunning for more cores with ArrowLakeRefresh top end SKUs.

So no source for anything you claimed. As usual, and as expected.

I thought this was a Zen 6 thread. I have heard nothing but the 8+32 Arrowlake from Intel in the last 2 pages.

Suppose we could talk about Zen 6 ?????

 

[poke01]

Suppose we could talk about Zen 6 ?????

No we can’t it seems. Every Zen thread must involve Intel, Nvidia and Apple/ARM. 😂

 

[Joe NYC]

So what will you use all that DDR6 bandwidth on then, if you think it'll only be 16C Zen6 for AMD? Will Zen6 consume 2x memory bandwidth compared to Zen5 per core?

APU.

If LPDDR6 manages to narrow the gap with GDDR, it will result in expanding market penetration of APUs in the notebooks and shrinking dGPUs in the notebook space.

 

[DAPUNISHER]

No we can’t it seems. Every Zen thread must involve Intel, Nvidia and Apple/ARM. 😂

Some compare and contrast is expected. But when it is turned into a vs thread, that's when it crosses the line. This thread crossed the line like it was a sprint. Cleaned it up a little. Hopefully the discussion will stay more on topic moving forward. If not, ban bingo cards will get filled.

And a reminder for those that seem confused. Speculating in a speculation thread is not against the rules. You cannot go after other members over their claims. If you take them seriously that's on you. The ignore feature exists for a reason. If someone is getting to you, use it. Don't go after them, that violates the first rule of fight club/CPU forum.

- Mod DAPUNISHER

 

[dr1337]

If Zen5 doesn't change core counts then I'm all in on Zen6 going straight to 32c for the flagship.

 

[itsmydamnation]

If Zen5 doesn't change core counts then I'm all in on Zen6 going straight to 32c for the flagship.

what is this super odd obsession........ what software??

im gonna by a 6 core Zen5 because im a cheap ass and im going to be happy and its going to murder all the workloads just fine.

 

[dr1337]

what is this super odd obsession........ what software??

im gonna by a 6 core Zen5 because im a cheap ass and im going to be happy and its going to murder all the workloads just fine.

All software? Lol lately I even get bottlenecked MT wise on a 5800X3D while gaming, and have to close out my browser if I want perfect minimums.

Also from a marketing perspective AMD is gonna want to compete with Intel on paper, at least for the top model. Giving up the core count crown for so many generations in a row is something they're bound to rectify IMO.

 

[itsmydamnation]

All software? Lol lately I even get bottlenecked MT wise on a 5800X3D while gaming, and have to close out my browser if I want perfect minimums.

Also from a marketing perspective AMD is gonna want to compete with Intel on paper, at least for the top model. Giving up the core count crown for so many generations in a row is something they're bound to rectify IMO.

If your running add block with chrome is probably the bs google has been pulling to make ads play on you tube. I'm surprised it doesn't get talked about more.

By you see you kinda jumps the shark from 8 to 32 cores and going well beyond sane scaling based of things like amdahs law.

 

[StefanR5R]

If Zen5 doesn't change core counts then I'm all in on Zen6 going straight to 32c for the flagship.

lately I even get bottlenecked MT wise on a 5800X3D while gaming, and have to close out my browser if I want perfect minimums.

Is it because game and browser are performing computation in more than eight normal-priority software threads combined? Or is it because the browser is GPU accelerated? (From what I understand, GPGPU task scheduling is not as intricate as CPU task scheduling, as far as realtime quality-of-service is concerned.) Edit: Or could it be RAM footprint actually? Though I imagine that would be a bigger issue than lacking minimal frame rate.

For latency issues, more bandwidth is in some but not all cases a solution.¹

On topic, there has been at least one poster in the Zen 5 speculation thread claiming that Zen 6 sticks with ≤16 cores (and ≤8 cores per CCX) in the client segment.

I do wonder if the Zen 6 uncore changes will make dual-CCX CPUs behave notably different to Zen 1…5 in moderately multithreaded applications like games in absence of last-level cache aligned CPU task scheduling policy. (Personally, I am not interested in games but in other occasional multithreaded applications with pronounced inter-thread data sharing.)

________
¹) Edit 2, to be clear, most of the times these are software issues, not lacking hardware. It is useful to recall that interactivity is all about bound latency, not about low latency per se, let alone about bandwidth. I am not into games, but my guess is that the usual stacks of operating system and game engine are not quite consequently architected as RTOSes. Or maybe this is the case on game consoles but not on Personal Computers?

 

[Joe NYC]

Is it because game and browser are performing computation in more than eight normal-
I do wonder if the Zen 6 uncore changes will make dual-CCX CPUs behave notably different to Zen 1…5 in moderately multithreaded applications like games in absence of last-level cache aligned CPU task scheduling policy. (Personally, I am not interested in games but in other occasional multithreaded applications with pronounced inter-thread data sharing.)

With RDL type packaging, it is possible for the 2 adjacent CCDs to have a direct link, which could allow, with some advanced algorithms for the CCDs to retrieve data from each other's L3.

Not as fast as from its own L3 but faster than from memory. Then if V-Cache was on both CCDs, there would be more data cached.

We will see if Strix Halo does anything in this area, even before Zen 6.

 

[adroc_thurston]

With RDL type packaging, it is possible for the 2 adjacent CCDs to have a direct link

That's not how cache coherency works on AMD parts.
On L3 miss you probe the c/sIOD directory and bang!