Question Zen 6 Speculation Thread

[gdansk]

Almost like comparing a server core paradigm to a mobile core paradigm.

And ARM has the same cadence as AMD in servers. But with bigger changes (so far). AMD is planning to slowly ship server cores for mobile at clocks outside of their efficiency range with a cache structure not designed for low power 1T use. It is not going to win the laptop market shipping an inferior product later. AMD doesn't even have a large foothold in that market and they won't win it doing thet. They'll be relegated to servers - a fate that has never worked out in the long run for VAX or various high-end RISCs.

Based on available plans Zen 5 is the last time AMD will be competitive in the laptop market. Which is sad because it was only a few years where they were relevant (5800U to HX 370) and it doesn't look like a market breakthrough is imminent.

 

[branch_suggestion]

Medusa mobile! But it'll be N3e and in early 2027.

Lame if true.
That means either N3P volume ramp is late or TSMC is charging an unreasonable premium vs N3E.
First AMD parts on N3P/N2 will be Venice/MI400 anyway, the complete death of Moore's Law means us proles won't get the shiny nodes outside of halo client stuff.

 

[branch_suggestion]

And ARM has the same cadence as AMD in servers. But with bigger changes (so far). AMD is planning to slowly ship server cores for mobile at clocks outside of their efficiency range with a cache structure not designed for low power 1T use. It is not going to win the laptop market shipping an inferior product later. AMD doesn't even have a large foothold in that market and they won't win it doing thet. They'll be relegated to servers - a fate that has never worked out in the long run for VAX or various high-end RISCs.

Based on available plans Zen 5 is the last time AMD will be competitive in the laptop market.

Just because ARM pumps out the IP fast doesn't mean actual finished products using said IP come out fast.
Comparing an IP vendor to a chip vendor is a flawed comparison.

 

[gdansk]

Just because ARM pumps out the IP fast doesn't mean actual finished products using said IP come out fast.
Comparing an IP vendor to a chip vendor is a flawed comparison.

That's true maybe MediaTek/Nvidia and Qualcomm will only cut a SoC for laptops every other generation. But the CAGR is still higher.

 

[FlameTail]

Okay who cares about cadence?

We got Apple, Intel and ARM who release chips every year because they make SMALL improvements to their core

Disagree with Apple and ARM only making small improvements YoY. CAGR is what matters.

Geekbench 6 Single Core	2022	2023	2024
ARM	2000 Cortex X3 (8G2)	2300 Cortex X4 (8G3)	2900 Cortex X925 (D9400)
Apple	2600  M2	3200  M3	4000  M4
Qualcomm			3200 Oryon-L (8E)
Intel	3100 13900K	3200 14900K	3400 285K
AMD	3000 7950X		3500 9950X

If this trend continues, ARM vendors will outpace x86 sooner than later.

I used Geekbench6 for convenenience, but I am sure this trend can been seen in SPEC2017 too.

Sure, ARM CPUs having 20% faster single core isn't going to lead them to taking 50% of the market overnight. X86 CPUs are protected by a moat of advantages such as compatibility and modularity. But what about the long term? Those advantages won't last for perpetuity. App compatibility on ARM is improving day by day, and one day there will be socketable desktop ARM CPUs.

X86 vendors will have to quicken their pace and/or deliver larger improvements with each generation, to keep up.

 

[branch_suggestion]

That's true maybe MediaTek/Nvidia and Qualcomm will only cut a SoC for laptops every other generation. But the CAGR is still higher.

Well a big part of the wait has been doing a big development shift, Medusa and Venice are far more divergent than Granite Ridge and Turin. Medusa is a proper laptop focused client platform, not just fiddled server handdowns. Venice can also focus on not having to cater to important client metrics and so have freedom to scale.
Good to wait and see how Strix Halo does before making big calls on the future.

 

[gdansk]

Good to wait and see how Strix Halo does before making big calls on the future.

That's true too. But if it performs like Zen 5 (and why wouldn't it?) we'll be stuck waiting 2 years for some Medusa that can't even match M4 Pro.

 

[adroc_thurston]

That means either N3P volume ramp is late or TSMC is charging an unreasonable premium vs N3E.

AMD just doesn't consider things not server as all that relevant.

Disagree with Apple and ARM only making small improvements YoY. CAGR is what matters.

Apple exhausted every available clkspeed steroid with M3/M4 and ARM threw nominal PPA out of the window with X5/925. 3.4mm^2 on N3e is not very bazinga.

 

[branch_suggestion]

But if it performs like Zen 5 (and why wouldn't it?)

Not so simple, 9800X3D yields nicely in cache bound workloads, Turin thanks to the upgraded sIOD and higher membw yields better than Granite Ridge.
Strix Halo removes the interconnect bottleneck and has more bandwidth per core, plus MALL should yield a bit but not nearly as much as the extended L3 of X3D.
So in productivity I believe Strix Halo will beat the 9950X at lower power, that is the claim I'll make and should bode well for Medusa.

 

[DrMrLordX]

AFAIR desktop will be based on mobile, not server anymore.

That's what @adroc_thurston told us, and it seems plausible. Nothing official from AMD yet (that I know of).

 

[adroc_thurston]

That's what @adroc_thurston told us, and it seems plausible. Nothing official from AMD yet (that I know of).

Yeah, it's all one platform now.
Hence why Granite is the last Ridge, but Range continues (Gator is after Fire).

 

[MS_AT]

Yeah, it's all one platform now.
Hence why Granite is the last Ridge, but Range continues (Gator is after Fire).

So is the GR last one with 512b SIMD units on client side?

 

[adroc_thurston]

So is the GR last one with 512b SIMD units on client side?

Not an ounce of idea.
But AMD is cheap and boy do they love reusing designs everywhere, so 4*512b going the way of the dodo is almost a safe bet.

 

[StefanR5R]

There are two connected questions:
– Will AMD choose to let SIMD throughput regress gen-on-gen in the top tier of client?
(If yes, that would be a first for Zen.)
– If no, can a next-gen narrower/ double-pumped SIMD implementation match throughput of the current gen implementation?
(Seems difficult.)

Edit:
Though if they improve on memory access bandwidth, a cut in SIMD execution bandwidth would mean a loss in small data footprint workloads but not necessarily in bigger data footprint workloads/ streaming workloads.

 

[fastandfurious6]

Gator Range sounds ominous 🤣 🐊🐊🐊

 

[moinmoin]

Okay who cares about cadence?

Cadence is essentially reaction time or latency. And if it's filler you can see a company scrambling for something to offer where the intended products didn't work out as planned (as it happened with Intel plenty of times in the past decade).

AMD is doing fine even on 16-22 month cadence.

No, at the higher end of this range it is not. There's a danger of AMD falling behind in CAGR, and the slower the cadence the harder it will be for AMD to catch up in CAGR.

I personally was hoping that the cadence entries running late would be subsequently followed by entries coming sooner, keeping the cadence average low. But that doesn't seem to be the case at all.

Apple exhausted every available clkspeed steroid with M3/M4

Compared to the previous M series gens M4 had some surprisingly solid IPC improvements on top of that though.

 

[LightningZ71]

I don't expect unified client to go forward with the full GR avx512 implementation and instead focus on affordable compatibility like Strix has. Honestly, that's a fine approach for the market and is miles more than Intel has done since Rocket Lake on client.

If they do improve CCD to IOD bandwidth, even with a reduced implementation, it should still be quite performant. If it makes client both more affordable AND allows the use of near cutting edge nodes, that's still a win.

 

[Meteor Late]

This IPC talk is meaningless, ARM players (including Apple and Qualcomm) have been rapidly increasing frequency in this timeframe, what I care about is performance improvement, not just IPC improvement. If they hit a frequency wall, they will put more effort into IPC than they have been doing now. The fact is that they are improving at a faster pace than AMD and Intel, AMD needs a faster cadence.

 

[MS_AT]

Not an ounce of idea.
But AMD is cheap and boy do they love reusing designs everywhere, so 4*512b going the way of the dodo is almost a safe bet.

That would be a shame for developers that would like to keep the software performant on two implementations. On the other hand they will have higher chance to get free performance from intel pushing AVX10/256 as AMD's own software attempts are... well not worth mentioning

If they do improve CCD to IOD bandwidth, even with a reduced implementation, it should still be quite performant

They would need to double SIMD mem load pipes to match zen5 mem load capabilities to use that boosted BW. If they would kept only two they would fall behind competition again (Lion has 3x256b load pipes)

 

[LightningZ71]

That would be a shame for developers that would like to keep the software performant on two implementations. On the other hand they will have higher chance to get free performance from intel pushing AVX10/256 as AMD's own software attempts are... well not worth mentioning



They would need to double SIMD mem load pipes to match zen5 mem load capabilities to use that boosted BW. If they would kept only two they would fall behind competition again (Lion has 3x256b load pipes)

I agree, increasing 256 bit throughput would be nice, and likely not as expensive as 512 bit pipes.

 

[OneEng2]

And ARM has the same cadence as AMD in servers. But with bigger changes (so far). AMD is planning to slowly ship server cores for mobile at clocks outside of their efficiency range with a cache structure not designed for low power 1T use. It is not going to win the laptop market shipping an inferior product later. AMD doesn't even have a large foothold in that market and they won't win it doing thet. They'll be relegated to servers - a fate that has never worked out in the long run for VAX or various high-end RISCs.

Based on available plans Zen 5 is the last time AMD will be competitive in the laptop market. Which is sad because it was only a few years where they were relevant (5800U to HX 370) and it doesn't look like a market breakthrough is imminent.

It Was a very different market when VAX and others fell. Today DC is the fastest growing and highest margin market for computing.

ARM based DC isn't close to competitive in most workloads today. It also lacks the PPA (really power per socket) needed to be competitive in the highly threaded DC workloads.

Seems to me AMD and Intel have quite a bit of room left here.

AMD just doesn't consider things not server as all that relevant.

Apple exhausted every available clkspeed steroid with M3/M4 and ARM threw nominal PPA out of the window with X5/925. 3.4mm^2 on N3e is not very bazinga.

One design shared over multiple markets focused on the highest growth and highest margin market. Seems like a good idea to me.

Not an ounce of idea.
But AMD is cheap and boy do they love reusing designs everywhere, so 4*512b going the way of the dodo is almost a safe bet.

Yea, like that other stupid company Toyota. Shared designs across multiple markets and products is so dumb (end sarcasm).

 

[adroc_thurston]

Compared to the previous M series gens M4 had some surprisingly solid IPC improvements on top of that though.

8% over 4 years is not good.
They did gain a lot of frequency though.

 

[FlameTail]

8% over 4 years is not good.
They did gain a lot of frequency though.

Dunno where you got 8% from. It's actually about 15% over 4 years (not including SME).

 

[soresu]

and ARM threw nominal PPA out of the window with X5/925

This was telegraphed years back in the Cortex X1 announcement where they outright stated PPA was no longer a goal for this lineage of cores.

They started off slower moving to 5 wide with X1, then got progressively chonkier from there.

 

[soresu]

On the other hand they will have higher chance to get free performance from intel pushing AVX10/256 as AMD's own software attempts are... well not worth mentioning

Eh?

AVX10/256 just gives parity to AVX512 for 256 bit instructions, plus whatever new instructions the 512 bit version is adding most likely.

If anything AMD putting AVX512 in Zen4 while Intel goofed it with Alder Lake has kept interest for it in some circles.