Question Zen 6 Speculation Thread

[Joe NYC]

Also wouldn't it be odd for mobile chips with razor tight margins to have SLC but not the DT chips.

As @adroc_thurston said, CPU's already have their own L3, which is faster, and AMD has a good method (V-Cache) to add more.

GPU can always use more cache. But also, CPU and GPU communicate by CPU writing to GPU's memory and then GPU using that data. The chances are it will still be in SLC. Which is more like adding more cache to the GPU.

What's the consensus on the IOD process node? I would suppose a GPU would really benefit from a new node if it is to also be part of the IOD. Is the GPU rumored to be in IOD or separate chiplet?

In Strix Halo, GPU is in the IOD. Which has major pros and cons.

Pros would be less friction in GPU accessing memory, and no further disaggregation
Cons: major one is using the most expensive node for parts of the die where much cheaper node would do just fine - analog / IO, SRAM.

I think the direction AMD is pressured to is to use advanced node for this IOD / SoC even for desktop - in order to improve the iGPU capability (to target corporate desktop) and to add NPU.

In ideal world, this "interposer" (MLID refers to) would be a base die on N7 (connected using Hybrid Bond), which would provide at the same time:
- the IOD functionality
- MALL SLC
- section of the base die under the CPU CCD could serve also serve as an independent V-Cache, allowing L3 SRAM to be removed from CCD, if every CCD is always be paired with a base die.

It would make a complete sense from POV of utilizing inexpensive N7 to great extend and using the expensive advanced node for (mostly) logic, taking advantage of continues density scaling for logic.

But the packaging capacity may be holding back this sort of bold move by AMD.

75mm2 CCD are surprisingly large even with 12 Cores.

SRAM in L2 and L3 don't scale so well, and if AMD is maintaining the same ratio of 4 MB L3 per core and 1MB (or more) L2 per core, it adds up with more cores.

 

[Joe NYC]

Well, it'a funny that some of this lines up with the drunken speculation I made several months ago:

Maybe this comment of mine was secretly one of MILD's sources for that video!

That's pretty good. What were you drinking?

 

[adroc_thurston]

In Strix Halo, GPU is in the IOD.

it's also that in Raphael lol.

 

[DisEnchantment]

As @adroc_thurston said, CPU's already have their own L3, which is faster, and AMD has a good method (V-Cache) to add more.

GPU can always use more cache. But also, CPU and GPU communicate by CPU writing to GPU's memory and then GPU using that data. The chances are it will still be in SLC. Which is more like adding more cache to the GPU.



In Strix Halo, GPU is in the IOD. Which has major pros and cons.

Pros would be less friction in GPU accessing memory, and no further disaggregation
Cons: major one is using the most expensive node for parts of the die where much cheaper node would do just fine - analog / IO, SRAM.

I think the direction AMD is pressured to is to use advanced node for this IOD / SoC even for desktop - in order to improve the iGPU capability (to target corporate desktop) and to add NPU.

In ideal world, this "interposer" (MLID refers to) would be a base die on N7 (connected using Hybrid Bond), which would provide at the same time:
- the IOD functionality
- MALL SLC
- section of the base die under the CPU CCD could serve also serve as an independent V-Cache, allowing L3 SRAM to be removed from CCD, if every CCD is always be paired with a base die.

It would make a complete sense from POV of utilizing inexpensive N7 to great extend and using the expensive advanced node for (mostly) logic, taking advantage of continues density scaling for logic.

But the packaging capacity may be holding back this sort of bold move by AMD.



SRAM in L2 and L3 don't scale so well, and if AMD is maintaining the same ratio of 4 MB L3 per core and 1MB (or more) L2 per core, it adds up with more cores.

I would have thought the L3 would be cut be in half considering same CCD would presumably be used for both Mobile and DT. So you are assuming 32M would be standard?
If it is really an Si interposer (325mm2?? ) and not Cu RDL on fan out, it should be possible to build wide and fast links and keep a lot of SLC on a non leading edge node, but keep the L3 at current 16M.

 

[adroc_thurston]

I would have thought the L3 would be cut be in half

halo and luggable parts have full L3 *right now*.

and not Cu RDL on fan out, it should be possible to build wide and fast links and keep a lot of SLC on a non leading edge node, but keep the L3 at current 16M.

Memside SLC will be pretty bad lat either way, not suitable for CPU usecases.

 

[Tuna-Fish]

Does it even make sense to feed a set of 2 * 12 hungrier-than-Zen-5 cores with dual channel DDR5?

By the time Zen6 is out, there should be CUDIMMs at 9600GT/s available as standard mid-to-high options, where 6000GT/s is today. That's a 60% boost right there.

 

[Doug S]

Costs go down over time FYI. N3e will cost significantly less in 2027 when N2 is expected to be out. In addition, TSMC is not going the only leader anymore since Intel has 18A, etc. More competition means lower prices for all.

Less, but definitely not "significantly" so.

 

[LightningZ71]

Assuming that the die sizes can be made to work, it would be notably cheaper to use CCXs with 16-24 MB of L3 (8-12 cores) with the needed vias for Vcache using N3e or even N3P, then just standardizing on low end parts having no Vcache and high end parts having it, both in Mobile and desktop. The Vcache die can move to N4C to keep costs lower but performance and size where it's needed.

Desktop can have, for example, 10600 with 16MB L3, 10600x with 80MB L3 (Vcache is 64MB here). 10700 can have 24MB with X having 88MB L3. 10900 can have 32MB L3, 10900x can have 160MB. Etc.

I realize that there will likely be a name change, but you get the idea.

 

[OneEng2]

Less, but definitely not "significantly" so.

It's impossible to really calculate, but I wonder what the fully loaded COST per wafer (including NRE burn down, amortized equipment costs (including setup and maintenance) overhead, etc) is for Intel's 18A?

N2 is GAA, but not BSPD. I suspect that 18A has even more process passes than N2.

I don't see how the process war can continue .... even for TSMC. The market value of a desktop or laptop (or mobile) processor is not changing significantly. In fact, one could argue it is going down as inflation has gone up while processor prices have not (as much).

 

[Doug S]

It's impossible to really calculate, but I wonder what the fully loaded COST per wafer (including NRE burn down, amortized equipment costs (including setup and maintenance) overhead, etc) is for Intel's 18A?

N2 is GAA, but not BSPD. I suspect that 18A has even more process passes than N2.

I don't see how the process war can continue .... even for TSMC. The market value of a desktop or laptop (or mobile) processor is not changing significantly. In fact, one could argue it is going down as inflation has gone up while processor prices have not (as much).

According to TSMC, the benefits of BSPDN in terms of reduced footprint (i.e. more chips per wafer) will pay for the additional cost of each wafer.

What processes are trailing edge phones using these days? Like for phones selling for $100? If they've made it to N7 or will be there in the next year or two then I think we've got a fair amount of runway left. Because if they can make the economics work there for a $100 device, there's a ton of room for further wafer price increases in the market for $1000 phones. Now that might eventually be something only Apple can afford and even premium Android phones are forced to stay on older/cheaper nodes but we're a long way from that day yet.

You'd see similar things in the PC market, the $250 doorbuster PCs might stay on older processes while the $1000+ models stay on the leading edge. For the really expensive stuff like $10K Xeons and $40K Blackwells they'll be able to stick it out even longer than Apple and the high end client PC market, though once they lose Apple's mass iPhone volume they'd have to start eating a lot more of the node and tool development cost per wafer.

 

[LightningZ71]

TSMC occassionally comes out with an "economy" priced node. N6 eventually served that purpose. They are currently pushing N4C as a cost reduced node that offers most of the features and capabilities of the N5/N4 family at a more economical price. Provided that they continue to do that going forward, that should keep the trailing edge of the market satisfied for a long time.

In addition, there's always Samsung. While they still have problems with their N-1 nodes, their N-2 or more nodes are reasonably matured and spec competitive with trailing nodes from their competitors. That will keep the low end market happy.

 

[Doug S]

TSMC occassionally comes out with an "economy" priced node. N6 eventually served that purpose. They are currently pushing N4C as a cost reduced node that offers most of the features and capabilities of the N5/N4 family at a more economical price. Provided that they continue to do that going forward, that should keep the trailing edge of the market satisfied for a long time.

In addition, there's always Samsung. While they still have problems with their N-1 nodes, their N-2 or more nodes are reasonably matured and spec competitive with trailing nodes from their competitors. That will keep the low end market happy.

What is level of "economy" though?

To make N6 they took N7 and over time tweaked the process a bit - streamlining it using a few layers of EUV (which was introduced with N7+) and optically shrinking it a bit so you get a few more chips per wafer and yields are mature so you get more working chips per wafer as well. AFAIK that's the economy, not the price they charge. I am skeptical the price decrease is any more than what was show in the table I posted above. i.e. you pay the same for N6 you do for N7, but you get a few more chips per wafer from it.

I mean, unless someone has evidence to the contrary, showing that N6 wafers are priced double digits less than N7 wafers. I don't know anything about N4C, if they actually removed some stuff that caused extra production steps they might be able to materially affect wafer prices in a way that N6 is unlikely to.

If instead of paying $20K for an N3 wafer like when it came out you're paying $16K five years later when it is N-2 I don't think that's enough to "keep the low end market happy". That's only reducing their cost by 20%. And that's a WAFER cost, when if they made the exact same design on the N-1 process they might pay 25% more but if they get 20% more chips per wafer its a pretty close call.

The cost advantage needs to overcome the dies per wafer advantage. Let's say you're doing the low end today and you're looking to use the N7 family (i.e. N6) to save money. You design something that requires 100 mm^2 and you can get X chips per wafer. If you compare that to using the N5 family (N4/N4P today, or N4C when it is available) if you took that SAME design maybe it is only 80 mm^2 on N4 so you get 20% more chips per wafer. Given that N5 only costs 30% more than N7 its a closer call than it looks.

 

[adroc_thurston]

The cost advantage needs to overcome the dies per wafer advantage. Let's say you're doing the low end today and you're looking to use the N7 family (i.e. N6) to save money. You design something that requires 100 mm^2 and you can get X chips per wafer. If you compare that to using the N5 family (N4/N4P today, or N4C when it is available) if you took that SAME design maybe it is only 80 mm^2 on N4 so you get 20% more chips per wafer. Given that N5 only costs 30% more than N7 its a closer call than it looks.

That's true for a generic SOC in spherical vacuum, but something like cIOD gonna have pretty poo chip-level scaling going from N6 to an N4 derivative.
It's basically paying premium for lower power (and/or newer IP).

 

[misuspita]

What is level of "economy" though?

To make N6 they took N7 and over time tweaked the process a bit - streamlining it using a few layers of EUV (which was introduced with N7+) and optically shrinking it a bit so you get a few more chips per wafer and yields are mature so you get more working chips per wafer as well. AFAIK that's the economy, not the price they charge. I am skeptical the price decrease is any more than what was show in the table I posted above. i.e. you pay the same for N6 you do for N7, but you get a few more chips per wafer from it.

I mean, unless someone has evidence to the contrary, showing that N6 wafers are priced double digits less than N7 wafers. I don't know anything about N4C, if they actually removed some stuff that caused extra production steps they might be able to materially affect wafer prices in a way that N6 is unlikely to.

If instead of paying $20K for an N3 wafer like when it came out you're paying $16K five years later when it is N-2 I don't think that's enough to "keep the low end market happy". That's only reducing their cost by 20%.

If you add inflation over the 5 years which it was increasing lately, it's more than 20%. But I guess this is the future we're heading for... No more cheap advanced lytho

 

[Thibsie]

That's true for a generic SOC in spherical vacuum, but something like cIOD gonna have pretty poo chip-level scaling going from N6 to an N4 derivative.
It's basically paying premium for lower power (and/or newer IP).

So I guess that in this case, id the power reduction isn't significant enough, the goal is to get as cheap as possible.

 

[LightningZ71]

Look at what AMD did with Mendocino. While their leading edge devices were 8 core monsters with massive transistor counts, Mendocino was a quad core product with a smaller iGPU using older, smaller cores produced on N6. From rough calculations, as compared to a full house Rembrandt chip or the soon to release Phoenix chip, you could get nearly 3x as many dies at excellent yields per wafer. That's a drastic cost savings.

That's the kind of thing I'm talking about.

 

[Meteor Late]

Look at what AMD did with Mendocino. While their leading edge devices were 8 core monsters with massive transistor counts, Mendocino was a quad core product with a smaller iGPU using older, smaller cores produced on N6. From rough calculations, as compared to a full house Rembrandt chip or the soon to release Phoenix chip, you could get nearly 3x as many dies at excellent yields per wafer. That's a drastic cost savings.

That's the kind of thing I'm talking about.

I hope AMD never does that again, these chips are BAD. I mean, it's perfectly fine to do cost saving chips on an older node. But to use Zen 2 in 2023 with only 2 CU in the iGPU, that's just terrible. A 4 core Zen 3 with 4 CU RDNA2 is not too much to ask with that older node.

 

[marees]

I hope AMD never does that again, these chips are BAD. I mean, it's perfectly fine to do cost saving chips on an older node. But to use Zen 2 in 2023 with only 2 CU in the iGPU, that's just terrible. A 4 core Zen 3 with 4 CU RDNA2 is not too much to ask with that older node.

Sonoma valley is mendocino succesor. Reportedly on Samsung 4nm

 

[Joe NYC]

I would have thought the L3 would be cut be in half considering same CCD would presumably be used for both Mobile and DT.

I think cutting the L3 dies in mobile monolithic chips are:
1. overall dies size and yields of large monolithic chips
2. AMD based laptop tended to be in the lower, more cost conscious end of the spectrum

Going with chiplets addresses #1, CPU CCD is still quite small
To be a player in higher of the laptop market probably dictates more performance, which full 32MB (or 48?) would deliver.

Well, there is a 3rd option - 24 MB. To have the same core to L3 ratio as before.

So you are assuming 32M would be standard?
If it is really an Si interposer (325mm2?? ) and not Cu RDL on fan out, it should be possible to build wide and fast links and keep a lot of SLC on a non leading edge node, but keep the L3 at current 16M.

The Si interposer of that size was sort of a dream scenario. Most likely not happening.

Also , it seems that MLID retracted that part of his leak (maybe somebody corrected him). The part about 325 mm2 interposer.

TLDR, his current explanation is that this would be a silicon bridge (which would imply short in length, only covering edges). The bridges would be similar in Venice, but maybe below not above...

Let's see if I can line up the video to that portion:

 

[OneEng2]

According to TSMC, the benefits of BSPDN in terms of reduced footprint (i.e. more chips per wafer) will pay for the additional cost of each wafer.

What processes are trailing edge phones using these days? Like for phones selling for $100? If they've made it to N7 or will be there in the next year or two then I think we've got a fair amount of runway left. Because if they can make the economics work there for a $100 device, there's a ton of room for further wafer price increases in the market for $1000 phones. Now that might eventually be something only Apple can afford and even premium Android phones are forced to stay on older/cheaper nodes but we're a long way from that day yet.

You'd see similar things in the PC market, the $250 doorbuster PCs might stay on older processes while the $1000+ models stay on the leading edge. For the really expensive stuff like $10K Xeons and $40K Blackwells they'll be able to stick it out even longer than Apple and the high end client PC market, though once they lose Apple's mass iPhone volume they'd have to start eating a lot more of the node and tool development cost per wafer.

It is my understanding that BSPDN is a significant cost increase to produce, and that it isn't a slam dunk across the board in PPA either (please correct me if I am off base here).

There are 2 cost items to consider with each die shrink. 1) NRE (one time development cost). 2) On-going process cost (cost per wafer).

You ALWAYS have to pay off the NRE, but once you do (usually several years of amortization), you are still left with the on-going process cost ..... forever.

The cost of NRE AND the cost of on-going process costs are going up exponentially while the benefit is already beyond the point of diminishing returns..... while the market price of the product for MOST products is not changing much at all.

This can't continue.... and honestly, I am quite sure it wont.

What is level of "economy" though?

To make N6 they took N7 and over time tweaked the process a bit - streamlining it using a few layers of EUV (which was introduced with N7+) and optically shrinking it a bit so you get a few more chips per wafer and yields are mature so you get more working chips per wafer as well. AFAIK that's the economy, not the price they charge. I am skeptical the price decrease is any more than what was show in the table I posted above. i.e. you pay the same for N6 you do for N7, but you get a few more chips per wafer from it.

I mean, unless someone has evidence to the contrary, showing that N6 wafers are priced double digits less than N7 wafers. I don't know anything about N4C, if they actually removed some stuff that caused extra production steps they might be able to materially affect wafer prices in a way that N6 is unlikely to.

If instead of paying $20K for an N3 wafer like when it came out you're paying $16K five years later when it is N-2 I don't think that's enough to "keep the low end market happy". That's only reducing their cost by 20%. And that's a WAFER cost, when if they made the exact same design on the N-1 process they might pay 25% more but if they get 20% more chips per wafer its a pretty close call.

The cost advantage needs to overcome the dies per wafer advantage. Let's say you're doing the low end today and you're looking to use the N7 family (i.e. N6) to save money. You design something that requires 100 mm^2 and you can get X chips per wafer. If you compare that to using the N5 family (N4/N4P today, or N4C when it is available) if you took that SAME design maybe it is only 80 mm^2 on N4 so you get 20% more chips per wafer. Given that N5 only costs 30% more than N7 its a closer call than it looks.

Pretty much see my post above again.

Look at what AMD did with Mendocino. While their leading edge devices were 8 core monsters with massive transistor counts, Mendocino was a quad core product with a smaller iGPU using older, smaller cores produced on N6. From rough calculations, as compared to a full house Rembrandt chip or the soon to release Phoenix chip, you could get nearly 3x as many dies at excellent yields per wafer. That's a drastic cost savings.

That's the kind of thing I'm talking about.

... and this is exactly the kind of thing that is needed to remain profitable for a company.

I hope AMD never does that again, these chips are BAD. I mean, it's perfectly fine to do cost saving chips on an older node. But to use Zen 2 in 2023 with only 2 CU in the iGPU, that's just terrible. A 4 core Zen 3 with 4 CU RDNA2 is not too much to ask with that older node.

If there is a price sensitive market you can meet with an older technology ..... why not?

 

[eek2121]

What is level of "economy" though?

To make N6 they took N7 and over time tweaked the process a bit - streamlining it using a few layers of EUV (which was introduced with N7+) and optically shrinking it a bit so you get a few more chips per wafer and yields are mature so you get more working chips per wafer as well. AFAIK that's the economy, not the price they charge. I am skeptical the price decrease is any more than what was show in the table I posted above. i.e. you pay the same for N6 you do for N7, but you get a few more chips per wafer from it.

I mean, unless someone has evidence to the contrary, showing that N6 wafers are priced double digits less than N7 wafers. I don't know anything about N4C, if they actually removed some stuff that caused extra production steps they might be able to materially affect wafer prices in a way that N6 is unlikely to.

If instead of paying $20K for an N3 wafer like when it came out you're paying $16K five years later when it is N-2 I don't think that's enough to "keep the low end market happy". That's only reducing their cost by 20%. And that's a WAFER cost, when if they made the exact same design on the N-1 process they might pay 25% more but if they get 20% more chips per wafer its a pretty close call.

The cost advantage needs to overcome the dies per wafer advantage. Let's say you're doing the low end today and you're looking to use the N7 family (i.e. N6) to save money. You design something that requires 100 mm^2 and you can get X chips per wafer. If you compare that to using the N5 family (N4/N4P today, or N4C when it is available) if you took that SAME design maybe it is only 80 mm^2 on N4 so you get 20% more chips per wafer. Given that N5 only costs 30% more than N7 its a closer call than it looks.

N6 could be had for under $7,000/wafer at one point, costs have increased a bit, but not much for the biggest customers.

I haven’t seen any charts showing pricing that is close to accurate. This is because all TSMC prices are negotiated. Nobody is paying $10,000 for N7, for example. Some are paying close to that for N5 variants.

That is based off what I have seen, at least. Who knows what things are like now.

 

[OneEng2]

N6 could be had for under $7,000/wafer at one point, costs have increased a bit, but not much for the biggest customers.

I haven’t seen any charts showing pricing that is close to accurate. This is because all TSMC prices are negotiated. Nobody is paying $10,000 for N7, for example. Some are paying close to that for N5 variants.

That is based off what I have seen, at least. Who knows what things are like now.

Agree, but the chart is likely a good reference to see the relative cost between nodes.

 

[Doug S]

Agree, but the chart is likely a good reference to see the relative cost between nodes.

Yeah that's kind of what I'm assuming. That it is like comparing LG OLEDs using MSRP. Depending on when you're buying you'll get pricing much less than MSRP, but the relative differences between the various sizes and model lines will remain roughly the same.

Just read something on wccftech (yeah I know) saying that TSMC is at 100% capacity for N5 and N3, and is going to increase prices on N5 to match supply and demand. Its good to be the king. If you look at the table I posted before you can see the previous price increase they did when they were at capacity post-covid.

 

[SteinFG]

Now that there's a rumor of 12C ccd for Zen 6, I kinda understand why AMD named their 12-core Zen 5 APU as 370 and not 390

 

[FlameTail]

The multicore performance of Medusa Point with 12 full-blooded Zen 6 cores is going to be terrific.

+50% faster than Strix Point.
+100% faster than Phoenix.