Question Zen 6 Speculation Thread

[Meteor Late]

The multicore performance of Medusa Point with 12 full-blooded Zen 6 cores is going to be terrific.

+50% faster than Strix Point.
+100% faster than Phoenix.

A bit optimistic I think. Unless you are talkiing about very high power limit, I don't see how.

 

[marees]

The multicore performance of Medusa Point with 12 full-blooded Zen 6 cores is going to be terrific.

+50% faster than Strix Point.
+100% faster than Phoenix.

How do we know that it is 12 "full blooded" zen 6 cores and not (4p + 8c) like Strix ??

After all the rumours also said that laptop design to be shared with desktop

 

[FlameTail]

CPU	Cores	Cinebench 2024 Multi
Ryzen AI HX 370	4 × Zen5 8 × Zen5C	1200
Ryzen 9900X	12 × Zen5	1750

If we assume Zen6 is 15% faster (+10% IPC, +5% clock), that means a 12-core Medusa Ridge will score ~2000.

A 12-core Medusa Point will not clock as high as the desktop counterpart, so let us subtract 10%, which gives ~1800 points. That's 50% higher than Strix Point.

 

[Meteor Late]

CPU	Cores	Cinebench 2024 Multi
Ryzen AI HX 370	4 × Zen5 8 × Zen5C	1200
Ryzen 9900X	12 × Zen5	1750

If we assume Zen6 is 15% faster (+10% IPC, +5% clock), that means a 12-core Medusa Ridge will score ~2000.

A 12-core Medusa Point will not clock as high as the desktop counterpart, so let us subtract 10%, which gives ~1800 points. That's 50% higher than Strix Point.
View attachment 112655

Yeah so you don't care about the power difference between HX 370 and 9900X? because that is the key metric here.
Again, maybe at like 80W power limit or something like that I could see it close to that, because at that point the 5c version starts being in a much worse point in the curve efficiency wise. But overall, 50% is a pipe dream with the same core count at reasonable power limits.

For what is worth, HX 370 1200 points is already at really high power limit iirc

 

[StefanR5R]

@FlameTail, Zen5 and Zen5c are exactly the same architecturally, and perform exactly the same. With some fineprint.

(The fineprint: Zen5c has a lower peak clock. Zen5c has a tiny bit better performance/Watt in workloads which are not sensitive to uncore parameters. Zen5 and Zen5c in StrixPoint differ WRT uncore: 4 cores sharing 16 MB L3$ versus 8 cores sharing 8 MB L3$.)

In workloads which are not particularly sensitive to uncore parameters, Zen5 in mobile and Zen5c in mobile have exactly the same iso-clock performance and almost the same iso-clock power draw, as long as they stay well beneath their f_max. The upshot: If your CPU-limited workload is power-limited, not clock-limited, then it almost doesn't matter if you have Zen5 or Zen5c or a mixture.

Vice versa, workloads which are sensitive to uncore parameters behave different on Zen5 and Zen5c because AMD chose to give them different uncore.

Cinebench is not particularly sensitive to how the uncore is set up, AFAIK. Especially not earlier Cinebenches; maybe it has changed a little with CB24 due to larger data footprint of the benchmark scene.

(More fineprint, but not directly impacting the Zen5-->Zen6 extrapolation: Zen5 in mobile differs from Zen5 in server. Zen5c in mobile differs from Zen5c in server. Zen5 in server is manufactured on a different process node than Zen5c in server.)

Of course it remains to be seen what strategies AMD will pursue WRT classic and dense cores in Zen 6 products. But there is little reason to suspect fundamental differences to how they chose to do it in the Zen 5 generation.

 

[Joe NYC]

How do we know that it is 12 "full blooded" zen 6 cores and not (4p + 8c) like Strix ??

After all the rumours also said that laptop design to be shared with desktop

Going from 8 full cores using N4 with die size of 70 mm2
to 12 cores on N2 (2 process node advance) with die size of 75 mm2

It seem very doable, especially considering that AVX-512 may go back to half width.

 

[adroc_thurston]

Going from 8 full cores using N4 with die size of 70 mm2
to 12 cores on N2 (2 process node advance) with die size of 75 mm2

It's not N2 lol.

 

[Saylick]

It's not N2 lol.

Zen 6 CCDs on N3P, but Zen 6C CCDs on N2?

 

[Joe NYC]

It's not N2 lol.

True. But still, if they cut AVX to half width, probably cut on board L3 from 32 MB to 24 MB on base models (without V-Cache), they could probably fit it in ~75 mm2 using N3.

 

[Joe NYC]

Zen 6 CCDs on N3P, but Zen 6C CCDs on N2?

Only the 32-core server chips would likely be on N2.

Who knows if these are going to be the "Dense" versions. Also, if all or majority of server chips will be suing the Dense versions.

 

[adroc_thurston]

Zen 6 CCDs on N3P, but Zen 6C CCDs on N2?

There are a few classic CCDs, but yes Venice dense is N2.

But still, if they cut AVX to half width, probably cut on board L3 from 32 MB to 24 MB on base models (without V-Cache),

They're not doing either. It's just an N3 freebie, which is .7x chip scaling or so.

 

[Kepler_L2]

True. But still, if they cut AVX to half width, probably cut on board L3 from 32 MB to 24 MB on base models (without V-Cache), they could probably fit it in ~75 mm2 using N3.

I don't think cutting AVX width and L3 cache is even necessary, N3 shrink to the cores + extra size (66->75mm²) + shrink to analog interfaces due to new packaging is enough to fit 12 cores.

 

[adroc_thurston]

I don't think cutting AVX width and L3 cache is even necessary

He just read too much into "DT and mobile got folded into client" and now projects the dreams. Stuff.

 

[poke01]

I don't think cutting AVX width and L3 cache is even necessary, N3 shrink to the cores + extra size (66->75mm²) + shrink to analog interfaces due to new packaging is enough to fit 12 cores.

It should be enough, Apple moved to 12P cores from 8 P cores when they went to N3.

Meanwhile Intel didn’t increase core count on N3 because the advantages of N3 were all used on Lion Cove size from ballooning even further.

 

[burninatortech4]

I hope AMD never does that again, these chips are BAD. I mean, it's perfectly fine to do cost saving chips on an older node. But to use Zen 2 in 2023 with only 2 CU in the iGPU, that's just terrible. A 4 core Zen 3 with 4 CU RDNA2 is not too much to ask with that older node.

This forum was speculating for a few years about a Zen 3 small die. Called "Monet". It never happened.

 

[Joe NYC]

I don't think cutting AVX width and L3 cache is even necessary, N3 shrink to the cores + extra size (66->75mm²) + shrink to analog interfaces due to new packaging is enough to fit 12 cores.

Good points, also about GMI links going away, freeing ups some die size.

I wonder if there is a dedicated version of Zen 5 for Strix Halo without GMI links or if it is reusing existing die.

 

[Joe NYC]

He just read too much into "DT and mobile got folded into client" and now projects the dreams. Stuff.

Would the dividing line be monolithic vs. chiplet? Where chiplet parts get the full functinality?

From the MLID description, these are all still aiming quite high end parts in the notebook space:
- Medusa Halo
- Medusa Point
Probably in top 10-25%, by price.

For desktop, full die would definitely be desirable.

And in more cost conscious laptop segments, served by monolithic parts, AMD could reduce L3 and AVX-512 width.

 

[adroc_thurston]

And in more cost conscious laptop segments, served by monolithic parts, AMD could reduce L3 and AVX-512 width.

Poverty stuffed is served by older gen parts.

 

[BorisTheBlade82]

Good points, also about GMI links going away, freeing ups some die size.

I wonder if there is a dedicated version of Zen 5 for Strix Halo without GMI links or if it is reusing existing die.

@adroc_thurston is on record for stating that they have a separate CCD.
I still find this a bit unbelievable for such a small volume part, but we will see.

 

[adroc_thurston]

I wonder if there is a dedicated version of Zen 5 for Strix Halo without GMI links

yeah.

I still find this a bit unbelievable for such a small volume part,

It's a relic from the era of strixes being tiled more or less.
Once upon a time, most strixes were that.

 

[FlameTail]

Everybody seems to be talking about the CCDs, but what about the IOD?

MLID said the Medusa Point IOD is about 200 mm², and made on N4 iirc.

That sounds somewhat dubious, because that's very large. For comparison, Strix Point is a monolithic 232 mm² N4 die.

Then Medusa Point would be 200 mm² N4 for IOD + 70 mm² N3 for CCD. That would be equivalent to about 300 mm² of N4 silicon, which is a 30% increase from Strix Point.

Even more dubiously, MLID claims that Medusa Point will have a 16 CU GPU. I suppose it depends on whether it's RDNA3.5 or UDNA.

If it's UDNA, then 16 CUs might be enough to compete against Panther Lake's 12 Xe3 GPU. If it's RDNA3.5, then 24 CUs might be needed. That would also explain why the IOD is so large.

 

[misuspita]

Could IOD be made on a bigger process? Like a dense N5? I think using N4 For such a big die would either imply they would need to use that on a higher number of cpus to recoup some costs, so basically... Everything that is not dirt cheap.

 

[adroc_thurston]

Like a dense N5? I think using N4

They're the same thing.

 

[Win2012R2]

MLID said

That sounds somewhat dubious

 

[CakeMonster]

If 12c is true, I'm very happy. Then I can probably live with the core parking mess in dual CCD CPU's, as they can handle my messy background stuff while gaming with 1 CCD. And if I want to encode or run AI at the same time, I'll take the additional hit as I do now anyway.