DDR5-9600 CUDIMMI wonder how is AMD going to feed 24 Zen6 cores on Granite Ridge.
Just faster DDR5. The main bottleneck currently is GMI3 anyway.I wonder how is AMD going to feed 24 Zen6 cores on Granite Ridge.
LPDDR6?
Big SLC on IOD?
Lineup based on chiplet-based APU featuring 12 * P-cores sounds weird.Would the dividing line be monolithic vs. chiplet? Where chiplet parts get the full functinality?
From the MLID description, these are all still aiming quite high end parts in the notebook space:
- Medusa Halo
- Medusa Point
Probably in top 10-25%, by price.
For desktop, full die would definitely be desirable.
And in more cost conscious laptop segments, served by monolithic parts, AMD could reduce L3 and AVX-512 width.
The term is "c", not "E". (In released AMD products, at least.)There surely are dies featuring E-cores too.
E-cores (C-cores or sense cores) only make sense on server where clock speeds are limited by TDP.It doesn't feel right. There surely are dies featuring E-cores too.
Frankly, it doesn't matter - its just not "the full core".The term is "c", not "E". (In released AMD products, at least.)
It is, just not the high speed one.Frankly, it doesn't matter - its just not "the full core".
The e/c cores are to reduce silicon cost. We will see them on desktop eventually from AMD as well.E-cores (C-cores or sense cores) only make sense on server where clock speeds are limited by TDP.
Even on mobile, C cores offer similar performance per watt as the regular cores (as David Huangs tests have shown), and actually worse or comparable performance per area. The reason for this is that the clockspeed reduction is greater than the area reduction.
There will be low power cores (not C cores) on the APU main dies, presumably, for idle purposes.
No? one is very power limited on mobile (Laptop), so a P core being able to reach 5GHz is meaningless in decently multithreaded workloads, as that would consume too much power at the power limit.Even on mobile, C cores offer similar performance per watt as the regular cores (as David Huangs tests have shown), and actually worse or comparable performance per area. The reason for this is that the clockspeed reduction is greater than the area reduction.
Doesn't make sense to put C cores on client desktop IMO. TDP is basically unlimited.The e/c cores are to reduce silicon cost. We will see them on desktop eventually from AMD as well.
I don't expect 12 full zen 6 cores per CCD, would be a pleasant surprise tho.
Yes, actually. Not 5 GHz MT, but around 4.5 GHz is doable with 60-80W TDP (typical windows laptop TDP). Versus 3 GHz-ish on C cores.No? one is very power limited on mobile (Laptop), so a P core being able to reach 5GHz is meaningless in decently multithreaded workloads, as that would consume too much power at the power limit.
You have your P cores for single or lightly threaded applications, where you can clock them very high and still be inside the power limit window. But, I don't see how 12 P cores instead of, say, 6 P cores and 6 c cores is useful at all for very paralel workloads, unless we are approaching 80W power limit maybe.
Performance per area advantage is meaningless in MT power limited scenario.
Big difference. Intel E-cores are totally different than P cores, and capability and speed.Lineup based on chiplet-based APU featuring 12 * P-cores sounds weird.
WTF 2026/2027 mobile lineup:
* high-TDP desktop replacement with X3D - Fire Range next - Zen 6 1-2 * 12P
* premium GPU performance - Medusa Halo - Zen 6 12P + large GPU
* premium APU - Medusa Point - Zen 6 12P + small GPU
* regular APU - a refresh of 2026 Strix Point refresh - Zen 5
* cheap APU - a refresh of 2026 Hawk Point refresh or Sonoma Valley - Zen 4 or Zen 5
It doesn't feel right. There surely are dies featuring E-cores too.
Doesn't make sense to put C cores on client desktop IMO. TDP is basically unlimited.
12 Z6 cores/CCD should be doable on N3, as others have said.
Yes, actually. Not 5 GHz MT, but around 4.5 GHz is doable with 60-80W TDP (typical windows laptop TDP). Versus 3 GHz-ish on C cores.
4.5/3 = +50% performance per core, full vs dense.
1/0.75 = -33% area, full vs dense.
Full is at the very least comparable to dense on mobile.
The e/c cores are to reduce silicon cost. We will see them on desktop eventually from AMD as well.
I don't expect 12 full zen 6 cores per CCD, would be a pleasant surprise tho.
And you'd pay for that right? Over a grand?They'd better have 3D cache on both chiplets and bigger...
A grand - no problems (and both chiplets better be same high quality!), can't see why it should cost more when 9800x3d is $479. I had to disable one non-3D chiplet on 7950x3d to get the perf I expected, so half the money wasted.And you'd pay for that right? Over a grand?
AMD's real cheap so if they can cut the area down for 'free', they will.Then, why do you think they would need to go with the dense cores?
area is money and boy does AMD love money.Doesn't make sense to put C cores on client desktop IMO.
A grand - no problems (and both chiplets better be same high quality!), can't see why it should cost more when 9800x3d is $479. I had to disable one non-3D chiplet on 7950x3d to get the perf I expected, so half the money wasted.
I can see only two good reasons for AMD not to offer it -
1) they'd rather have 2 happy customers with 9800x3d than 1
2) highly clocked 16 core with so much cache might work as a very nice cheap server part and thus compete with their overpriced Epycs that offer extra cache by virtue of having lots of chiplets with 32 MB each
I'd most likely still buy single cache 9950x3d but only if 3D chiplet clocks better than 9800x3d.
Overpriced Epyc? They are selling in droves. Clearly people think they are worth the money.
I would.And you'd pay for that right? Over a grand?
If placing cache below active cores is reliable enough, then they could go away with L3 in core level entirely and shrink dies accordingly ...And you'd pay for that right? Over a grand?
Everybody seems to be talking about the CCDs, but what about the IOD?
MLID said the Medusa Point IOD is about 200 mm², and made on N4 iirc.
That sounds somewhat dubious, because that's very large. For comparison, Strix Point is a monolithic 232 mm² N4 die.
Then Medusa Point would be 200 mm² N4 for IOD + 70 mm² N3 for CCD. That would be equivalent to about 300 mm² of N4 silicon, which is a 30% increase from Strix Point.
Even more dubiously, MLID claims that Medusa Point will have a 16 CU GPU. I suppose it depends on whether it's RDNA3.5 or UDNA.
If it's UDNA, then 16 CUs might be enough to compete against Panther Lake's 12 Xe3 GPU. If it's RDNA3.5, then 24 CUs might be needed. That would also explain why the IOD is so large.