Question Zen 6 Speculation Thread

[MS_AT]

AVX10.1/256 is AVX512VL without the 512-bit registers. That is, AMD already implements it, it's a subset of AVX512.

I really hope they will not drop AVX512 support and that they support will AVX10/512 (if I am not mistaken this implies that AVX10/256 will also be supported) on client cores. I mean they already have superior physical implementation regardless if we look at half or full rate. I think it would be a waste if they dropped 512b support on client cores [I would have preferred they would keep full rate, but if they deem it too much, I really hope 512b half-rate will be used] as this is giving the advantage back to intel for seemingly no gain.

 

[Win2012R2]

AVX10.1/256 is AVX512VL without the 512-bit registers. That is, AMD already implements it, it's a subset of AVX512.

Yes, but if there are no 512 bit registers then how would legacy AVX-512 work on that CPU? Double pumping still (I think) required full registers - if /256 isn't compatible with AVX-512 then it's DOA

I really hope they will not drop AVX512 support

That would be an incredibly stupid thing to do now that it finally gets proper traction in software support, and results are great already.

Even if AVX10.2 is great, it will appear like when sometime in 2026? Who knows how Intel will look like by that point

 

[Win2012R2]

What I am trying to say that to keep AVX512 vs AVX512 half-rate vs AVX10/256 is not an easy decision.

That's easy - keep full AVX512 or go home

 

[gdansk]

They can abandon 512 bit registers and add more 256 bit execution units. This would allow increased throughput for 128/256 bit operations and still have the same throughput (but with more latency) for 512 bit operations. But I think it takes more transistors overall.

 

[Win2012R2]

They can abandon 512 bit registers

Would that still work with AVX-512 code?

 

[gdansk]

Would that still work with AVX-512 code?

Yes, I mean going back to a Zen 4 like AVX-512 but with the load/store bandwidth increases of Zen 5 and more execution units + larger queues so there could be more "double pumped" operations in flight at the same time.

It should be better for client workloads and also still be good for HPC. And on c cores they could not add the extra FPU pipes/queues to further save area if they wanted to cheap out (and I think they do).

 

[GTracing]

Yes, I mean going back to a Zen 4 like AVX-512 but with the load/store bandwidth increases of Zen 5 and more execution units + larger queues so there could be more "double pumped" operations in flight at the same time.

It should be better for client workloads and also still be good for HPC. And on c cores they could not add the extra FPU pipes/queues to further save area if they wanted to cheap out (and I think they do).

Double pumping doesn't reduce the size of the registers. Double pumped AVX-512 requires the full 512 bit registers.

 

[Win2012R2]

"It is worth noting that despite Intel AVX10/512 including all of Intel's AVX-512 instructions, applications compiled to Intel AVX-512 with vector lengths limited to 256-bit are not guaranteed to work with an AVX10/256 processor due to differences in the supported mask register width."

Intel Unveils AVX10 and APX Instruction Sets: Unifying AVX-512 For Hybrid Architectures

www.anandtech.com

Just more problems, double pumping is great approach, this is just more problems.

 

[OneEng2]

This is wrong on so many levels I'm gonna weep.

Sure does, Granite Ridge still shares the core CCD design with Turin Classic.

Please explain the price pressure you feel AMD and Intel feel in DC chips. Intel just released Granite Rapids which underperforms Turin by a significant margin and still is priced significantly higher. Can you provide some evidence to the contrary?

Good point on Granite Ridge, but I am unsure if this will continue going forward with Zen 6.

 

[gdansk]

Double pumping doesn't reduce the size of the registers. Double pumped AVX-512 requires the full 512 bit registers.

Does it? I thought they paired two registers together and presented it as ZMM. Since they have way more than 32 registers internally - for rename - I'm not sure.

 

[DrMrLordX]

Yeah... is it a good thing though?

Maybe. Unification of CCD design between desktop and server meant that desktop would always be dragged forward into the future no matter what, but brought with it power consumption penalties and GMI link limitations. Separating the two gives AMD more opportunities to neglect desktop if they feel it is to their advantage. Or we may just get more-efficient design that target end users better than repurposed workstation parts.

It doesn't today with Turin D which has a bunch of N3E based 16 core CCDs.

The core design is the same. Regardless, Turin does share CCDs with Granite Ridge, so (for now) the legacy continues.

 

[GTracing]

Does it? I thought they paired two registers together and presented it as ZMM. Since they have way more than 32 registers internally I'm not sure how it would be distinguishable anyway.

[with double pumping] they can implement the 16 x 256-bit registers of AVX2, but only need to implement 128-bit floating point and integer units. This comes with a cost: while you save on die space and power, some workloads may see significant performance regressions.

AVX10/128 is a silly idea and should be completely removed from the specification

Intro and lots of context

chipsandcheese.com

 

[gdansk]

AVX10/128 is a silly idea and should be completely removed from the specification

Intro and lots of context

chipsandcheese.com

So it must be. But the general idea remains. 2x execution units but double pumped allows more throughput in existing software without hurting AVX-512 throughput (it would hurt latency). And since they'll have more logic transistors to play with it seems like that path forward for AMD (unless it totally explodes scheduling and register file ports)

 

[adroc_thurston]

Please explain the price pressure you feel AMD and Intel feel in DC chips

CSPs literally make their own (heavily subsidized by ARM) stuff lmao.

Intel just released Granite Rapids which underperforms Turin by a significant margin and still is priced significantly higher

>list prices
you can't be this new can you

 

[OneEng2]

AVX10/128 is a silly idea and should be completely removed from the specification

Intro and lots of context

chipsandcheese.com

Thanks!

The part I particularly want to point out is this one:

In other words, you should expect implementations to use AVX10.N with 512-bit vectors. This ensures that any existing AVX-512 code is fully supported, and continues the legacy of backward compatibility for x86_64.

CSPs literally make their own (heavily subsidized by ARM) stuff lmao.

>list prices
you can't be this new can you

... and you believe that ARM competes with high end x86 servers today? Also, creating your own CPU costs lots and lots of money. Unless you make a metric crap ton of them, it doesn't pay off.

Yes, list prices. It is pointless to discuss it any other way. There is no way to know how OEM deals are structured between companies and how much CPU unit price is agreed on.

You should have more class than to belittle someone as you did. I am not, in fact, "new" at all and have been a PC enthusiast since the TRS80 was introduced. Show a little respect. These are all interesting conversations to have, and disagreements can be had without disrespect.

 

[Thunder 57]

Thanks!

The part I particularly want to point out is this one:

In other words, you should expect implementations to use AVX10.N with 512-bit vectors. This ensures that any existing AVX-512 code is fully supported, and continues the legacy of backward compatibility for x86_64.

... and you believe that ARM competes with high end x86 servers today? Also, creating your own CPU costs lots and lots of money. Unless you make a metric crap ton of them, it doesn't pay off.

Yes, list prices. It is pointless to discuss it any other way. There is no way to know how OEM deals are structured between companies and how much CPU unit price is agreed on.

You should have more class than to belittle someone as you did. I am not, in fact, "new" at all and have been a PC enthusiast since the TRS80 was introduced. Show a little respect. These are all interesting conversations to have, and disagreements can be had without disrespect.

I had to look up the TRS80. I don't even think my parents had met when it came out, let alone me existing.

It would be nice if people would be a bit more respectful here. This isn't Reddit or WCCFTech and I think most would like to keep at that way. Sorry for the OT.

 

[reaperrr3]

You're not getting that either. Double wide stuff is squarely for -halo.

Makes me wonder if boards with soldered-on Medusa-Halo will come to desktop anyway, as literal premium halo product.

Because if there's no downsides to core count, core clocks, V-Cache etc. and twice the memory bandwidth, I can absolutely see some enthusiasts and semi-professionals being willing to pay 1K+ if that gets them twice the RAM bandwidth and a beefy IGP.

 

[adroc_thurston]

Makes me wonder if boards with soldered-on Medusa-Halo will come to desktop anyway, as literal premium halo product

Don't need a board when you can build a NUC. But that's still hella niche.

 

[Win2012R2]

and a beefy IGP

To hell with IGP - pair it with 6090!

As long as it gets at least 64 GB, bare minimum

 

[Joe NYC]

they did that. Just uh, not in client. You guys are too poor for SoIC everywhere.

I have not noticed before, but it looks like AMD has a higher ASP on the DIY side than Intel. Primarily due to SoIC chips.

BTW, there was a time, just past the Zen 3 release, when Lisa said that she wants to make AMD into a premium brand. That was a little short lived, after:
- Alder Lake release
- delay of 5800x3d way past Alder Lake release
- Rembrandt debacle (partially caused by DDR5 only choice at the time of weak market)

Maybe AMD is trying again in client market - with Zen 5 V-Cache, Strix Halo.

If AMD sells required enough high ASP parts, more products with SoIC will become possible. One obvious such part would be Strix Halo with full graphics, one CCD and V-Cache - for gaming Mini PCs

https://twitter.com/x/status/1873310847063245066

 

[MS_AT]

They can abandon 512 bit registers and add more 256 bit execution units. This would allow increased throughput for 128/256 bit operations and still have the same throughput (but with more latency) for 512 bit operations. But I think it takes more transistors overall.

The register file is already partitioned on Strix, meaning that there are more 256b entries than 512b entries available for rename. The cleverness of Zen4/Zen5 half-rate 512b implementation depends on the fact that they are tracking the instruction as single uOP through the pipeline and the split is only happening at the execution unit, in contrast with Zen1 implementation of AVX2, where AVX2 ops were internally split into 2 128b uops and were carried out as if they were 2 separate instructions. So in theory if I understood your proposal it should work, but for some reason AMD decided not to go with that route. I mean it might be that with AVX2 you would not be able to make efficient use of those execution units due to architectural register limit. Or that the control structures for the additional execution units were more trouble than they are worth.

 

[fastandfurious6]

I have not noticed before, but it looks like AMD has a higher ASP on the DIY side than Intel. Primarily due to SoIC chips.

BTW, there was a time, just past the Zen 3 release, when Lisa said that she wants to make AMD into a premium brand. That was a little short lived, after:
- Alder Lake release
- delay of 5800x3d way past Alder Lake release
- Rembrandt debacle (partially caused by DDR5 only choice at the time of weak market)

Maybe AMD is trying again in client market - with Zen 5 V-Cache, Strix Halo.

If AMD sells required enough high ASP parts, more products with SoIC will become possible. One obvious such part would be Strix Halo with full graphics, one CCD and V-Cache - for gaming Mini PCs

https://twitter.com/x/status/1873310847063245066

yeah alder lake literally saved intel, the last 'fast' architecture from them and they have nothing significantly 'better' even in the pipeline... arrow lake is par with alder even worse in some cases

amd is already working on zen 6 and it will be significantly faster than zen 5

 

[Nothingness]

CSPs literally make their own (heavily subsidized by ARM) stuff lmao.

Do you really think Arm has the money to heavily subsidize hyperscalers? They might get some interesting reduction, but it's unlikely to reach the level Intel can afford. Anyway lower cost is only part of the reason why Arm makes inroads in that market (TCO goes beyond chip price, flexibility to add accelerators on SoC, etc.).

 

[gdansk]

Do you really think Arm has the money to heavily subsidize hyperscalers?

Yes, ARM can easily afford not to charge royalties in markets into which it wants to expand.

They're even able to spend on luxury lawsuits to punish a customer who torpedoed their NVDA stock deal.

 

[Nothingness]

Yes, ARM can easily afford not to charge royalties in markets into which it wants to expand.

Do you really think royalties amount to several thousands dollars per SoC?