No, but who said they need that? They're cheaper than they will be in the future is the point. I.e. the price pressure actually alleviates with ARM's market share growth which is the opposite of the argument given.
No, but who said they need that? They're cheaper than they will be in the future is the point. I.e. the price pressure actually alleviates with ARM's market share growth which is the opposite of the argument given.Do you really think royalties amount to several thousands dollars per SoC?
ARM CSSDo you really think Arm has the money to heavily subsidize hyperscalers? They might get some interesting reduction, but it's unlikely to reach the level Intel can afford.
Source for the faster part?amd is already working on zen 6 and it will be significantly faster than zen 5
That's literally what they do yes, they pay for every bit of the difficult difficult core/SoC R&D and charge hyperscalers about treefiddy for it.Do you really think Arm has the money to heavily subsidize hyperscalers
I think right now ARM is getting on average like 7 cents per chip or something like that, but they wanted to switch to model where they get a %-tage of end chip price, not sure that worked out for them. Either way based on some pricing info from Ampere their server chips are so expensive that might as well use AMD instead without any compatibility hassles.Do you really think royalties amount to several thousands dollars per SoC?
Source for the faster part?
Zen 6 is an evolutionary design based on Zen 5, just like Zen 2 and Zen 4 are. AMD puts Zen 6 IPC goal to 10-15%. The frequency bump is questionable since we are already at ~6GHz. Increasing the core count from 16c is expected but the scaling of client apps is not really great.
It was in leaked slide that later appears to have been confirmed as genuinedid they announce 10-15% goal?
It was in leaked slide that later appears to have been confirmed as genuine
Except someone will get so bored by the lack of progress that their wandering mind will be jolted by a sudden spark of creativity and voila! A new door opens!I think we need to start getting used to smaller improvements and longer times between generations. Damn Physics!
Note: This problem only applies to x64 in the near term. Apple and ARM will keep delivering decent improvements every year until they hit the power and frequency wall. Probably only a few years later but still.I think we need to start getting used to smaller improvements and longer times between generations.
Fits the range of 10-15Not exactly, it was listed as 10%+.
Hopefully they will fix dual branch predictor, it's possible it does not work that well due to cuts in transistor budget on 4nmZen 6 will get some improvement in density
Fits the range of 10-15
With greatly diminishing probability for each +1%, where as 10%+ makes it very likely to be in range of 10-15% (mid is only 12.5%), but a lot less so to be in 10-20%Sure, but it also allows for it to be outside that range.
With greatly diminishing probability for each +1%, where as 10%+ makes it very likely to be in range of 10-15% (mid is only 12.5%), but a lot less so to be in 10-20%
Since Zen 5 underperformed (I reckon dual branch predictor not working as intended so in effect it's less wide than Zen 4) - if that's fixable and gets fixed in Zen 6 then maybe we will see better improvement than on that slide.
I'll be happy if they add Intel APX to it
That's true.I was just pointing out that the slide didn't actually state that range whereas for Zen 5
With greatly diminishing probability for each +1%, where as 10%+ makes it very likely to be in range of 10-15% (mid is only 12.5%), but a lot less so to be in 10-20%
Since Zen 5 underperformed (I reckon dual branch predictor not working as intended so in effect it's less wide than Zen 4) - if that's fixable and gets fixed in Zen 6 then maybe we will see better improvement than on that slide.
I'll be happy if they add Intel APX to it
I think the biggest issue is the dual decoder not helping in single thread - which may be a bug or an incomplete feature.
Mike Clark in one interview stated that both decoders should work in single thread (which was incorrect as far as shipping Zen 5), so maybe it is there but disabled.
You have to wonder how much this would add to single thread code...
On a plus side - if they do so well with 4-wide decoder and another one disabled in non-SMT mode, then imagine how much better it will be with just 5-wide decoders? Maybe primary (most likely branch) decoder should be 5-6 wide and secondary is 4-wide...
Could also be the massive uOP cache keeping the core fed without being held back by the decoders so much.
Yeah it stalls on int prf's mostly (aka the thing that saw the smallest (basically none) growth).From the (granted limited) publicly available profiling done on Zen 5, the decoder width was seldom the bottleneck for the Zen 5 core.
As @Hitman928 stated the profiling of Zen 5 done so far had revealed the frontend bandwidth - decoders busy, uOp busy - is NOT the bottleneck. The frontend latency - a L1i cache miss, fetch after a mispredicted branch, ITLB misses, etc. - often is.I think the biggest issue is the dual decoder not helping in single thread - which may be a bug or an incomplete feature.
Mike Clark in one interview stated that both decoders should work in single thread (which was incorrect as far as shipping Zen 5), so maybe it is there but disabled.
You have to wonder how much this would add to single thread code...
The slide contains marketing speak since the slide was not internal but presented under NDA. This means they definitely do not need to sandbag or anything like that.I agree that the highest probability lies in the 10%-15% range, I was just pointing out that the slide didn't actually state that range whereas for Zen 5, they did give that range with an upper limit, which means they're leaving it a bit more open to possibly getting higher IPC for Zen 6, even if it's not likely.