Question Zen 6 Speculation Thread

[MS_AT]

Unfortunately I can't find a chart right now which enumerates which resources are partitioned statically vs. dynamically in AMD's current SMT implementation.

A table can be found in optimization manual, unfortunately I don't have the means to access it right now.

I don't know. The clever people left and formed their own company?

Since we are in AMD thread I meant AMD

 

[yottabit]

Since AVX512 is apparently too fast for its own memory and AVX256 is too slow…

I propose AVX384. It only works with 48 and 96 GB DIMMs

Intel, AMD, anyone want to hire me?

 

[fastandfurious6]

Intel is currently producing wack P cores..

all investors need to know!

 

[igor_kavinski]

How many believe that Zen 6 will have SMT4? I mean, since their SMT2 works so well (up to 40%), it's only right that they should try increasing the core resource utilization even more by going up to 60% perf uplift through SMT4.

 

[Tuna-Fish]

No-one who's paying any attention to the market?

 

[OneEng2]

When it comes to Zen6 wishlist it is suprising nobody wants them to allievate actual bottlenecks in Zen5 beside too small int reg file.

I actually believe that aside from adding more cores, that this is ALL AMD will do on Zen 6. They will tweak the bottlenecks that can be tweaked with little increase in transistor count, have a faster memory controller with lower latency, and put all this together to make Zen 6 IMO.

How many believe that Zen 6 will have SMT4? I mean, since their SMT2 works so well (up to 40%), it's only right that they should try increasing the core resource utilization even more by going up to 60% perf uplift through SMT4.

Naw. Going from NO SMT to SMT2 has pretty good dividends (in this case 15% more transistors for 40% more performance.

Going from SMT2 to SMT4 would require a very significant increase in transistor count and might only yield an additional 10% OVER SMT2 (as a wild guess).

IBM Power 10 has 8 way SMT. It scales really well, but has a die size of >600mm2.... and how many of those are sold? From what I have read, it is less power efficient, and less performant that Turin across the board.

 

[LightningZ71]

Going wider than SMT2 puts a lot of strain on the processor's caches. To get any sort of notable gains from it, you need a very wide core with excessively large caches that is notably heavy in memory utilization.

 

[igor_kavinski]

you need a very wide core

Wider than Skymont?

What about Zen 6's front end? Is there a chance that AMD will do full 8-wide design instead of 4+4 or even 10 wide?

 

[Win2012R2]

Is there a chance that AMD will do full 8-wide design instead of 4+4 or even 10 wide?

No chance... AMD said Zen 5 is their new foundation and they will built upon it, plus it seems that very wide Intels design is not yielding that much more, I reckon 5+5 with working dual branch prediction without SMT might be very very nice.

 

[LightningZ71]

There's always a possibility that anything can happen. However, I don't see AMD going 8 wide any time soon, unless it's some fancy bonding technique between both 4+4 decoders. What could happen is going to a pair of 6 + 6 wide decoders. While I wouldn't want to be any part of the team designing it, it is technically possible that both of them could be handling 2 threads each. Things start to get rapidly more complicated, you suddenly double all of your statically assigned resources and also double the demand on your shared resources, leading to a likely choice to duplicate more of them, which then starts to balloon your chip size further.

All of that for MAYBE a 10% gain in ideal situations and higher power utilization on your front end and a massively more difficult validation process. You rapidly get to a point where four simpler cores would typically be more performant AND cost effective. IBM Power is a very heavily targeted special case.

 

[MS_AT]

Wider than Skymont?

What about Zen 6's front end? Is there a chance that AMD will do full 8-wide design instead of 4+4 or even 10 wide?

Zen5 is 8-wide design, as it is 8 wide at rename and if you are running from uop cache you are able to sustain 8 instr in flight

I think they should borrow some fetch tricks from Apple before they widen the decode width. To ensure they minimise waste time on decoding instructions on not taken path.

 

[HurleyBird]

Wider than Skymont?

What about Zen 6's front end? Is there a chance that AMD will do full 8-wide design instead of 4+4 or even 10 wide?

I'd guess within a few generations it becomes 4+4+4, similar to Intel's e-core trajectory.

 

[Win2012R2]

Zen5 is 8-wide design

No, it isn't: 4+4 (especially with not working second decoder in non-SMT scenario - according to Cheese&Chips) is not the same as 8 wide fully available for single thread. It was clearly designed to push SMT with some hope it can be made work also without, but does not seem to be the case at the moment. I hope they will upgrade it to 5+5 at least, or maybe they should just go to 6 wide single and be done with it, I hate SMT with a passion.

 

[Hulk]

With Intel failing so badly why should AMD try hard with Zen 6? They might as well take it easy and keep a few tricks up their sleeve should they need them if Intel does wake up.

Unfortunately the reality of Intel falling so far behind will undoubtedly a more relaxed AMD.

 

[Win2012R2]

With Intel failing so badly why should AMD try hard with Zen 6?

Because only paranoid survives? Seems like a good enough reason to me

They'll just charge premium for even better product, also good enough reason, plus a lot of Zen 6 key work must have been more or less finished by now

 

[Joe NYC]

With Intel failing so badly why should AMD try hard with Zen 6? They might as well take it easy and keep a few tricks up their sleeve should they need them if Intel does wake up.

Unfortunately the reality of Intel falling so far behind will undoubtedly a more relaxed AMD.

AMD has less than 20% of client market and only about 34% of server market.

There is certainly no time to relax until those percentages are flipped.

 

[JustViewing]

No, it isn't: 4+4 (especially with not working second decoder in non-SMT scenario - according to Cheese&Chips) is not the same as 8 wide fully available for single thread. It was clearly designed to push SMT with some hope it can be made work also without, but does not seem to be the case at the moment. I hope they will upgrade it to 5+5 at least, or maybe they should just go to 6 wide single and be done with it, I hate SMT with a passion.

It is 8 MacroOp wide. That means at peek it can execute 16 instructions.

For Zen 3 I was able to execute nearly 10 instructions per clock

http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=thread...ical-discussion.2619688/page-14#post-41282969

 

[Win2012R2]

It is 8 MacroOp wide. That means at peek it can execute 16 instructions.

Not when per thread decoder can only decode 4, your chart says that very clearly: 1T: 4 instructions per cycle, 8 will only work in SMT, which is why Zen 5 got better than usual uplift in it.

There is certainly no time to relax until those percentages are flipped.

Intel won't survive (as it is now) if or when AMD hits 50%, which it might do in servers soon if 18A is a bust

 

[MS_AT]

No, it isn't: 4+4 (especially with not working second decoder in non-SMT scenario - according to Cheese&Chips) is not the same as 8 wide fully available for single thread. It was clearly designed to push SMT with some hope it can be made work also without, but does not seem to be the case at the moment. I hope they will upgrade it to 5+5 at least, or maybe they should just go to 6 wide single and be done with it, I hate SMT with a passion.

You are wrong. Reread the articles you mention. Since most of the time code is being executed from uop cache that can dispatch 12 uop to rename, the decode throughput is less important. If you want further confirmation read Zen5 optimization manual to learn how decode and uop cache interact with each other.

And Alex Yee tested that when mixing SIMD and integer code you can in fact reach 8 inst per cycle without SMT.

 

[JustViewing]

Not when per thread decoder can only decode 4, your chart says that very clearly: 1T: 4 instructions per cycle, 8 will only work in SMT, which is why Zen 5 got better than usual uplift in it.

No, 1 thread Zen 5 can work at peek throughput when instructions are coming from Op Cache which is majority of time. What you are mentioning only valid for dual decoder and not for Op Cache. As I linked above, Zen 3 can execute ~10 uOps/Cycle with an IPC of 7.7. For Zen 5 it should be higher.

 

[adroc_thurston]

Zen 3 can execute ~10 uOps/Cycle with an IPC of 7.7

Only with like fused NOPs.
The actual renamer width is just ~six~.

 

[JustViewing]

Only with like fused NOPs.
The actual renamer width is just ~six~.

Incorrect, please check the test I did. I am not saying it is practical in real world scenarios, but possible in useless code.
http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=thread...ical-discussion.2619688/page-14#post-41282969

 

[Win2012R2]

No, 1 thread Zen 5 can work at peek throughput when instructions are coming from Op Cache which is majority of time.

Ok, it's getting above my pay grade. But I will correct you on the peAk bit though!

when mixing SIMD and integer code you can in fact reach 8 inst per cycle without SMT

How often does that happen in existing code? It does seem exotic to me

Either way I hope decoder goes up at least +1 for Zen 6

 

[DrMrLordX]

With Intel failing so badly why should AMD try hard with Zen 6? They might as well take it easy and keep a few tricks up their sleeve should they need them if Intel does wake up.

Unfortunately the reality of Intel falling so far behind will undoubtedly a more relaxed AMD.

Intel let down their guard and look what happened to them. You never know who is out to get you.

 

[MS_AT]

How often does that happen in existing code? It does seem exotic to me

Everytime when you are using mixed integer and floating point computations. Scalar FP is handled by the SIMD unit anyway. In SIMD heavy code you still need to use scalar int part of the core to generate addresses and handle loop control.

So probably the only time it does not happen is when running scalar int only code.

I mean in terms of opportunities to make full use of the machine width, of course waiting for data etc results in lower ipc.