Question Zen 6 Speculation Thread

[GTracing]

And they could just use a separate smaller and cheaper 8 core CCD for the Ryzens 3 and 5.

I think it's more likely that the cheapest CPUs will be monolithic and maybe use an older node. If they ditch the NPU and cut back the GPU, they could get the die size under 150mm^2

 

[Thunder 57]

I say pretty great. I think 4 cores are insufficient in this day and age. My prediction about Zen 6 line-up:

Ryzen 3 6C/12T
Ryzen 5 8C/16T
Ryzen 7 10700X 10C/20T
Ryzen 7 10800X 12C/24T
Ryzen 9 10900X 20C/40T
Ryzen 9 10950X 24C/48T

When was the last time was saw a Ryzen 3? The 3100 and 3300X which were basically vapourware?

6 out of 12 cores defective seems like there wouldn't be enough of them to sell!

They don't have to be defective. Like Mark said they could disable them. Back in the day Phenom II X3 and X2 could have cores re-enabled if they weren't defective. That has not been possible for a long time though as they have ways to make them permanently disabled.

I think it's more likely that the cheapest CPUs will be monolithic and maybe use an older node. If they ditch the NPU and cut back the GPU, they could get the die size under 150mm^2

Maybe for the low end AMD uses laptop APU's like they did with the 5600G. They could go monolithic APU for 6 & 8 cores then chiplet for 10+. 10 or 12 (one CCD), 16, 20, 24 (dual CCD). That's a lot of SKUs though so maybe less variants.

Of course that could cause confusion. There would be less L3 cache on the APU's and far weaker iGPU's on the chiplet models. I don't think it's that big of a deal though. Six and eight cores are far more likely to be basic office machines where a beefier iGPU would be welcome. Higher end models most would prefer the extra L3 cache for performance and are far more likely to be paired with a dGPU anyway.

 

[GTracing]

Maybe for the low end AMD uses laptop APU's like they did with the 5600G. They could go monolithic APU for 6 & 8 cores then chiplet for 10+. 10 or 12 (one CCD), 16, 20, 24 (dual CCD). That's a lot of SKUs though so maybe less variants.

Of course that could cause confusion. There would be less L3 cache on the APU's and far weaker iGPU's on the chiplet models. I don't think it's that big of a deal though. Six and eight cores are far more likely to be basic office machines where a beefier iGPU would be welcome. Higher end models most would prefer the extra L3 cache for performance and are far more likely to be paired with a dGPU anyway.

I was picturing a small iGPU for the budget mobile CPU, like how Phoenix 2 has 4CU. If they are unifying desktop and mobile I imagine they'll have different IO dies for different market segments. They could have a midrange mobile IO die with support for one CCD and a large iGPU.

 

[Thunder 57]

I was picturing a small iGPU for the budget mobile CPU, like how Phoenix 2 has 4CU. If they are unifying desktop and mobile I imagine they'll have different IO dies for different market segments. They could have a midrange mobile IO die with support for one CCD and a large iGPU.

Good point, I didn't think of that.

 

[LightningZ71]

On Ryzen 3: Are we forgetting the 5xxx series?
OEM only 5100
APUs: 5300ge, 5300g
Mobile: 5400u, 5125c, 7330u

Or Zen4:
8300G, GE
7440u
8440u

Granted, except for the OEM 5100, all of the rest were a repurposed APU. I wouldn't be shocked to see Kraken Point APUs appear in the Ryzen3 space at some point.

 

[Thunder 57]

On Ryzen 3: Are we forgetting the 5xxx series?
OEM only 5100
APUs: 5300ge, 5300g
Mobile: 5400u, 5125c, 7330u

Or Zen4:
8300G, GE
7440u
8440u

Granted, except for the OEM 5100, all of the rest were a repurposed APU. I wouldn't be shocked to see Kraken Point APUs appear in the Ryzen3 space at some point.

Yes I did forget them. My guess is because exactly as you said, they were repurposed APUs.

 

[Thibsie]

I thought they were no difference in L3 between desktop and APUs for Zen4 ?

 

[SteinFG]

I thought they were no difference in L3 between desktop and APUs for Zen4 ?

The same difference as in Zen 3 generation. Ryzen 7000 is 32MB L3, Ryzen 8000G is 16MB L3

 

[Thibsie]

The same difference as in Zen 3 generation. Ryzen 7000 is 32MB L3, Ryzen 8000G is 16MB L3

Damn, I thought I read here on this forum somewhere that there wouldn't be a difference for Zen4 variants.

No difference would make it easy to repurpose APUs without much practical difference.

 

[igor_kavinski]

Interesting comment here: https://www.overclock.net/posts/29425812/

A more direct example would be that Zen 5's front-end is statically partitioned and makes it's SMT implementation a lot like CMT in some ways. The actual execution isn't split and and, when required, one front-end can take advantage of a core that is much wider than it would usually be able to serve because of giant modern op-caches.

Could this mean that Zen 6's SMT will be even more like CMT since Mike Clark hinted that they laid the foundation for the future in Zen 5?

 

[Kepler_L2]

Interesting comment here: https://www.overclock.net/posts/29425812/



Could this mean that Zen 6's SMT will be even more like CMT since Mike Clark hinted that they laid the foundation for the future in Zen 5?

It's the opposite of CMT. Two front-ends sharing one back-end, rather than two back-ends sharing one front-end.

 

[OneEng2]

And they could just use a separate smaller and cheaper 8 core CCD for the Ryzens 3 and 5.

Doesn't make as much sense because its lots of validation and tooling for something you can get mostly just by yield binning requirements of a 12 core CCD.

Doing the design on a completely different process would, not only require tons of validation, but would actually require a parallel design. Really not worth it.

They could just disable them.

Good point.

 

[StinkyPinky]

I say pretty great. I think 4 cores are insufficient in this day and age. My prediction about Zen 6 line-up:

Ryzen 3 6C/12T
Ryzen 5 8C/16T
Ryzen 7 10700X 10C/20T
Ryzen 7 10800X 12C/24T
Ryzen 9 10900X 20C/40T
Ryzen 9 10950X 24C/48T

That would be amazing, but since AMD is curb stomping Intel at the moment I wonder if they really have the incentive to do a 20 core 10900X and sell it cheaper than a 16 core 9950X.

 

[OneEng2]

That would be amazing, but since AMD is curb stomping Intel at the moment I wonder if they really have the incentive to do a 20 core 10900X and sell it cheaper than a 16 core 9950X.

I think it will more come down to supply and demand for AMD. If they are yielding well and get lots of good 20 and 24 core parts from the two 12 core CCD chiplets, then we can expect prices to reflect this. It's also the same for the 10 and 12 core single CCD variants.

 

[Kepler_L2]

I think it will more come down to supply and demand for AMD. If they are yielding well and get lots of good 20 and 24 core parts from the two 12 core CCD chiplets, then we can expect prices to reflect this. It's also the same for the 10 and 12 core single CCD variants.

I think with 12 core CCD it makes sense to have 3 different bin targets. Right now the only have full (8 core) and 6 core bins. With 12 core CCD they could have full (12 core), 10 core and 8 core.

So the lineup could be

10950X - 24 cores
10900X - 20 cores
10700X - 12 cores
10600X - 8 cores

or

10950X - 24 cores
10900X - 16 cores
10700X - 12 cores
10600X - 10 cores

 

[Thunder 57]

I think with 12 core CCD it makes sense to have 3 different bin targets. Right now the only have full (8 core) and 6 core bins. With 12 core CCD they could have full (12 core), 10 core and 8 core.

So the lineup could be

10950X - 24 cores
10900X - 20 cores
10700X - 12 cores
10600X - 8 cores

or

10950X - 24 cores
10900X - 16 cores
10700X - 12 cores
10600X - 10 cores

With the first set there is a large gap between 12 and 20 cores. With the second, I have a hard time believing AMD's lowest offering would suddenly be a 10 core. If I had to guess I'd pick the first.

 

[poke01]

I think with 12 core CCD it makes sense to have 3 different bin targets. Right now the only have full (8 core) and 6 core bins. With 12 core CCD they could have full (12 core), 10 core and 8 core.

So the lineup could be

10950X - 24 cores
10900X - 20 cores
10700X - 12 cores
10600X - 8 cores

or

10950X - 24 cores
10900X - 16 cores
10700X - 12 cores
10600X - 10 cores

Will the top AMD Zen6 part be on par with the 48 core NVL part?

Same thread count.

 

[Kepler_L2]

Will the top AMD Zen6 part be on par with the 48 core NVL part?

No, assuming 16+32 actually launches.

 

[HurleyBird]

No, assuming 16+32 actually launches.

We're also assuming no Zen6c CCX on the Range IOD, despite that one probably exists on the Point IOD, all assuming MLID is right about everything going chiplets.

Worst case it's possible MLID or his sources are counting Zen6c cores on the IOD as belonging to the CCD, where Medusa point could be 8 Zen6 on the CCD + 4 Zen6c on the IOD.

 

[Kepler_L2]

We're also assuming no Zen6c CCX on the Range IOD, despite that one probably exists on the Point IOD, all assuming MLID is right about everything going chiplets.

Worst case it's possible MLID or his sources are counting Zen6c cores on the IOD as belonging to the CCD, where Medusa point could be 8 Zen6 on the CCD + 4 Zen6c on the IOD.

Cores on the IOD are Zen6LP not Zen6c. Also it's clear just from the shape of the CCD in the leaked diagrams that core count has increased.

 

[HurleyBird]

Cores on the IOD are Zen6LP not Zen6c.

Yeah, LP branding is assumed. But are those just Zen6c derivatives with a bit of optimization, or a whole other thing?

The degree to which they are useful for added compute rather than simple background tasks will mostly come down to cache hierarchy.

Also it's clear just from the shape of the CCD in the leaked diagrams that core count has increased.

Cool.

 

[soresu]

That would be amazing, but since AMD is curb stomping Intel at the moment I wonder if they really have the incentive to do a 20 core 10900X and sell it cheaper than a 16 core 9950X.

For tech enthusiasts like us that need to know everything about perf before we purchase that curb stomping is self evident.

To the average consumer though all they see is Ghz and core count, and maybe the TDP if they are power conscious.

 

[Timorous]

I say pretty great. I think 4 cores are insufficient in this day and age. My prediction about Zen 6 line-up:

Ryzen 3 6C/12T
Ryzen 5 8C/16T
Ryzen 7 10700X 10C/20T
Ryzen 7 10800X 12C/24T
Ryzen 9 10900X 20C/40T
Ryzen 9 10950X 24C/48T

I see 8c as a minimum, possibly even a cache cut part for the 12c CCDs that have defects here there and everywhere.

If you want fewer than 8 cores just buy Zen 5 because they won't stop making those for a while. Maybe that is when they release a 9600X3D part once the 9800X3D is knocked off the perch as the fastest gaming CPU by the 11800X3D.

I suspect the stack will be as follows. Naming will be 11000 probably unless AMD change the established pattern, which would be a very AMD thing to do.

R9 11950X3D 24c
R9 11900X3D 20c
R7 11800X3D 12c
R7 11700X 10c
R5 11600X 8c

I don't see the point in AMD offering a non X3D 12c part. People will just wait for the X3D version since it will be the gaming king and even if Zen 6 is amazing there will be games where the extra v-cache still matters more. Maybe as an OEM special but in the DIY market nah, a bit pointless.

I also don't see the point in non X3D versions of the R9 parts unless there is a time to market issue. Again maybe OEM offerings will have non X3D parts but for DIY not so sure I can see the point.

As for the v-cache I suspect the 12c CCD will have 48MB L3 cache to keep the cache/core ratio the same and as such I also suspect the v-cache CCD will now sport 96MB L3 providing a total L3 cache of 144MB which will be a nice bump from the 96MB L3 the 9800X3D gets you. Wonder how much further that will allow people to push stuff like Factorio and Stellaris before they exceed the cache pool and become more memory bound again.

 

[LightningZ71]

I don't see them keeping the L3 cache levels the same. L3 cache is NOT shrinking as well as everything else and they are already increasing the number of cores by 50%. In addition, we have relatively solid information that this CCD will be used on mobile as well as desktop, so having that amount of cache is going to be prohibitive.

This is what I expect:
The cache die will switch to N4C as it's node.
The 12 core CCX will move to 24MB L3, keeping the mobile cache ratio of 2MB per core.
Every CCD will be able to have 3D cache at manufacturing time, though some will fail/disable this function.
The desktop parts will be in two series, a non-x series and an X3D series. The non-x parts will be economy priced and have no 3d cache. The X3D parts will.

I expect mobile will have a value monolithic part for the Ryzen 3 and 5 line, maybe 4p+4c. There will be a mainstream H line, which is similar to current Halo with 1 or 2 CCDs with no 3d cache. The HX line will be similar, but with 3d cache. Halo is differentiated by the io die with large iGPU.

I expect the 9 series to have 24 and 20 core parts, both with and without 3d cache. While there is room for a 16 core part, I don't see the value in that, maybe for OEMs.

The 7 series will be for top of the line 12 core CCDs.
The 5 series will be 8 core CCDs
The 3 series will more than likely be monolithic mobile parts.

Intel's move to have a base die with a lot of cache will force AMD'S hand here. They won't be able to be competitive at higher price points without 3d cache.

I don't think that reducing the L3 on the CCD will hurt as much due to the improved communications between the CCDs and the IOD for the lower end parts, in addition, 24MB is still more than the existing 16MB on mobile parts.

 

[CakeMonster]

What are the estimated failure rates? If its the same as Zen4/5, you'd expect CCD's with 9c enabled, not 10c for the lower binned parts.