Question Zen 6 Speculation Thread

[Hail The Brain Slug]

What are the estimated failure rates? If its the same as Zen4/5, you'd expect CCD's with 9c enabled, not 10c for the lower binned parts.

At some point recently someone from AMD said even the 6 core chiplets are just artificially disabled cores, yields are too good

 

[basix]

Failure rate will be minimal for a 70mm2 CCD. Disabling 2 or 3 cores will not make a relevant yield difference. 8/10/12C just makes more sense regarding portfolio setup. 20C for the 2x CCD entry as well, 16C is too close to 12C, you need to spend an additional CCD and get some disadvantages due to the dual CCD setup.

 

[HurleyBird]

This is what I expect:
The cache die will switch to N4C as it's node.
The 12 core CCX will move to 24MB L3, keeping the mobile cache ratio of 2MB per core.
Every CCD will be able to have 3D cache at manufacturing time, though some will fail/disable this function.
The desktop parts will be in two series, a non-x series and an X3D series. The non-x parts will be economy priced and have no 3d cache. The X3D parts will.

Nah.

If the CCD has a cache die by default, then 24MB is still consuming way too much die space. I'd expect something close to 0.

The two most likely scenarios are that they keep L3 at 32 or go up to 48.

 

[Timmah!]

Just found out about this 12C CCD for Zen6. Is it just a rumor, or confirmed to be a thing? If its confirmed, i am definitely skipping Zen5 - there was still small possibility i would consider getting 9950x3D, but i wont if its guaranteed to be replaced by 24C chip in 2 years or so.

 

[GTracing]

Just found out about this 12C CCD for Zen6. Is it just a rumor, or confirmed to be a thing? If its confirmed, i am definitely skipping Zen5 - there was still small possibility i would consider getting 9950x3D, but i wont if its guaranteed to be replaced by 24C chip in 2 years or so.

It's just a rumor. It makes sense, but people here have been way off before. *cough *cough Zen5 40%

 

[basix]

Nah.

If the CCD has a cache die by default, then 24MB is still consuming way too much die space. I'd expect something close to 0.

The two most likely scenarios are that they keep L3 at 32 or go up to 48.

32MByte is unlikely to happen with 12C. With 12C you want to have 12 cache connections and therefore also 12 cache slices (design, performance and symmetry reasons). 32MB does not divide evenly by 12
GPUs like GB202 are looking different because the cache setup is not the same (GPU = MALL cache = fixed ratio towards memory interface // CPU = fixed ratio towards cache clients)

I'd like to see 48MByte on Zen 6 but what about 36MByte (3MB/Core)? This is more than 32MByte today (=gaming performance) and keeps Die area for cache moderate if not small (Zen 5's 32MByte are only ~15mm2 in size).

For APUs you could stay at 36MByte (AI HX or whatever that is called nowadays) and/or salvage the thing down to 24MByte.

And:
Zen 6 with 12C will very likely feature a monolithic CCD. This thing won't be big enough to make Die stacking beneficial for regular CCDs.

 

[LightningZ71]

Die stacking is still a non-trivial expense and still adds to the power draw of the CCD/cache combo. It is strongly rumored that mobile and desktop will be using the same CCDs, with server and low end mobile being different. If that's the case, they still needs there to be product differentiation up and down the stack. This means that they need to be able to use CCDs that don't meet binning requirements in other ways, and having any L3 at all on the CCD is still important to enable that.

Since SRAM is scaling slower than logic, it makes sense to reduce it on the CCD going forward, but it still needs to be sufficient to the task. 2MB per core is adequate for lower stack items, and is also easily divisible in binary. It also follows AMD's mobile strategy.

I do suspect that the 3d cache die will grow in capacity from switching to N4C, and suspect that it will be 128MB, giving a total of 152MB of L3 per CCD stack. That's an important mark to hit if Intel tops out at a rumored 144MB.

 

[yuri69]

All those theories... AMD will most probably go the cheapest and most incremental way possible. I don't think they would stay on 8c tho. So maybe 10c?

Anyways, do we know how the >8c CCX works? Was there any slide depicting the 16c Turin Dense CCX in detail? Any topology or latency analysis done by the C&C guys?

----

Btw die stacking is still quite bad since it requires booking additional packaging capacity, additional manufacturing steps including additional shipping and testing. This adds cost and makes the lead time per processor longer.

 

[eek2121]

*cough *cough Zen5 40%

…That was caused by different individuals having different products in mind causing confusion. Many here think “client” like Ryzen, but server is the chip to look at.

There are a few other things at play as well, but I did want to point that out.

 

[uzzi38]

Anyways, do we know how the >8c CCX works? Was there any slide depicting the 16c Turin Dense CCX in detail? Any topology or latency analysis done by the C&C guys?

C&C haven't had hands on with it yet, unfortunately. All their testing so far on Zen 5c was using Strix Point. Our best chance at getting that information is probably the upcoming ISSCC presentations next week, or HotChips later on in the year. Hopefully the former.

 

[Joe NYC]

Nah.

If the CCD has a cache die by default, then 24MB is still consuming way too much die space. I'd expect something close to 0.

The two most likely scenarios are that they keep L3 at 32 or go up to 48.

If both are true that:
- Zen 6 CCD is 12 cores
- Zen 6 is N2, down to client and this 12 core CCD

Then it would make sense to have no L3 on main CCD and always pair this expensive N2 CCD with inexpensive die with V-Cache as "pair node" as in this patent.

https://twitter.com/x/status/1848609092685729923

 

[Kepler_L2]

If both are true that:
- Zen 6 CCD is 12 cores
- Zen 6 is N2, down to client and this 12 core CCD

Then it would make sense to have no L3 on main CCD and always pair this expensive N2 CCD with inexpensive die with V-Cache as "pair node" as in this patent.

https://twitter.com/x/status/1848609092685729923

While this would be cool I don't think it's happening yet. The size of the CCD is ~75mm², minus the die-to-die interface and test/debug circuitry that's around 60mm², or 5mm² per core if the CCD had no L3. That's a humongous core on N2.

 

[Timorous]

While this would be cool I don't think it's happening yet. The size of the CCD is ~75mm², minus the die-to-die interface and test/debug circuitry that's around 60mm², or 5mm² per core if the CCD had no L3. That's a humongous core on N2.

If it had 36MB L3 and scaling is rubbish we could say it will be 15mm just like the 32MB slab in Zen 5 is so that leaves 45mm for cores which means 3.75mm/core

 

[branch_suggestion]

If both are true that:
- Zen 6 CCD is 12 cores
- Zen 6 is N2, down to client and this 12 core CCD

Then it would make sense to have no L3 on main CCD and always pair this expensive N2 CCD with inexpensive die with V-Cache as "pair node" as in this patent.

https://twitter.com/x/status/1848609092685729923

Yeah that patent is cracked, Z7 stuff using BSPDN to do deranged things.
Could see the cache changing with this arrangement.
Venice is just CCDs stacked on AIDs with the same SoIC-L interconnect.

 

[GTracing]

…That was caused by different individuals having different products in mind causing confusion. Many here think “client” like Ryzen, but server is the chip to look at.

There are a few other things at play as well, but I did want to point that out.

Fair enough, but if the 12 core rumor has the same amount of caveats, then we should assume the worst for all possible unknowns. The 12 core CCD exists, but 8 of the 12 cores are dense and only clock to 4GHz, and the L3 cache per core is cut in half, and the AVX pipeline is double pumped.

 

[Hitman928]

…That was caused by different individuals having different products in mind causing confusion. Many here think “client” like Ryzen, but server is the chip to look at.

There are a few other things at play as well, but I did want to point that out.

It was more individuals taking full threaded server results and trying to derive the core IPC from it and then (at least some) pretending like they had IPC numbers directly from AMD and mocking anyone who doubted their number. Even after it was revealed that the number was derived, they continued to insist it was accurate and mock naysayers who said that they shouldn't try to derive the IPC like that because it wouldn't be accurate. In the end, it wasn't even close.

 

[LightningZ71]

I hadn't considered the possibility that each CCD could be a mix of different core types. AMD has certainly done that before. If they keep the same size ratio between the cores, they could do 6 P cores and 6 C cores and only grow the physical dimensions just a little while also keeping the L3 cache at 32MB. I don't necessarily think that they would want to do 4+8 as that may not game bench as well, but doing so would almost preserve the same footprint as 8 P cores. Comparing the 9700x to the AI 370, the vast majority of the performance difference between the two is caused by the lower clocks of the 370, the larger L3 of the 370, and everything being on one CCX. If AMD had done a 12 core Zen5 CCX with 4 + 8, the ST would be the same and the MT for it would likely be higher for that as compared to the 9700x.

That's a very interesting thought...

 

[Thibsie]

/me wonders who will be the first idiot YouTuber doing an ST test pinned to a C core and claim AMD is beaten by Intel.

Popcorn incoming.... 🤣

 

[Kepler_L2]

If it had 36MB L3 and scaling is rubbish we could say it will be 15mm just like the 32MB slab in Zen 5 is so that leaves 45mm for cores which means 3.75mm/core

Latest data from TSMC has N2 SRAM density at +50% over N5

Edit: Sorry it's actually +50% over N7, +18% over N5

 

[Timorous]

Latest data from TSMC has N2 SRAM density at +50% over N5

Edit: Sorry it's actually +50% over N7, +18% over N5

View attachment 116911

Any clue what logic scaling is like from N4? I tried to find some info on it but couldn't find anything.

 

[Kepler_L2]

Any clue what logic scaling is like from N4? I tried to find some info on it but couldn't find anything.

~20% logic density over N3, which is is 60% logic density over N5 (~50% over N4).

 

[Markfw]

/me wonders who will be the first idiot YouTuber doing an ST test pinned to a C core and claim AMD is beaten by Intel.

Popcorn incoming.... 🤣

what I don't get is why Intel people do not understand that an AMD c core is the same as regular except runs slower. (and maybe less cache ??)

 

[igor_kavinski]

what I don't get is why Intel people do not understand that an AMD c core is the same as regular except runs slower. (and maybe less cache ??)

Most of them don't WANT to understand

If they had the desire to understand, they wouldn't have kept buying Raptor Lake.

 

[Joe NYC]

Latest data from TSMC has N2 SRAM density at +50% over N5

Edit: Sorry it's actually +50% over N7, +18% over N5

View attachment 116911

While price of N2 will be up to 4x, which would be paying 4x but receiving only 1.5x.

Which means the value proposition for stacking SRAM on a cheap mode improves. We may already be in the area where cost of stacking equal amount of SRAM on stacked die is cheaper than keeping it on main die. (after the overhead of stacking)

But if you consider that the separate die can hold 3x to 4x SRAM, then the increase of L3 size is gravy.

 

[Kepler_L2]

While price of N2 will be up to 4x

It's more like 2.5x the price of N7