Question Zen 6 Speculation Thread

[adroc_thurston]

The point is that AMD needs to increase clock rates with Zen 6.

They don't 'need to'. It's a thing that comes free (sort of). With a shrink!

It'll be lucky to offer M4-tier performance

N3e 3-2. Not comparable.

 

[poke01]

never^2 since validating SMT on yearly cadence is asking for trouble

oh they release ~500mm2 SoCs every year. Their validation team is decent.

No one else does that

 

[gdansk]

They don't 'need to'. It's a thing that comes free (sort of). With a shrink!

No, they need to. Otherwise it's merely a ghetto core by 2026Q4 standards. Increasing fmax would take work. But it seems they figured it is easier than increasing IPC.

 

[adroc_thurston]

oh they release ~500mm2 SoCs every year

That's not the hard part.

Their validation team is decent.

Ehhh.

No one else does that

I'm gonna wham! your head with the good ol' golden age era Intel tick-tock.
Not only they did stuff yearly, they also threw shrinks at the problem!

 

[poke01]

Ehhh

why? what happened?

 

[adroc_thurston]

No, they need to

?

Otherwise it's merely a ghetto core by 2026Q4 standards

every non-N2 core in 2026Q4 will be 'ghetto'. Hope that helps!

Increasing fmax would take work.

It's literally free.

But it seems they figured it is easier than increasing IPC.

Increasing IPC is trivial. Doing that while maintaining IPC/CAC delta is, well.

why? what happened?

They don't have a tough task, just a lot of it.

 

[poke01]

I'm gonna wham! your head with the good ol' golden age era Intel tick-tock

Intel did not release consumer 500mm2 SoCs yearly come on

 

[adroc_thurston]

Intel did not release consumer 500mm2 SoCs yearly come on

They sure did lmao (well, server. but chungus still), everything from Woodcrest until Haswell-EP was a yearly march unto greatness.

 

[poke01]

Otherwise it's merely a ghetto core by 2026Q4 standards

This is assuming others won't also be meh. AMD will be fine. We should be worry about Intel's P core

 

[gdansk]

This is assuming others won't also be meh. AMD will be fine. We should be worry about Intel's P core

No, Apple could still be shipping M4 and still be better than Medusa.
Intel is not really anything I'd be concerned about.

 

[adroc_thurston]

Apple could still be shipping M4 and still be better than Medusa.

delulu

 

[poke01]

Apple could still be shipping M4 and still be better than Medusa.

idk, zen6 has some good packaging as well N2. M6 Pro/Max might be than better than Medusa Halo but not M4.

 

[gdansk]

idk, zen6 has some good packaging as well N2. M6 Pro/Max might be than better than Medusa Halo but not M4.

Nope, do the 1T math. Strix is ~2950 at 5.1GHz. Assume the best case scenario for Medusa: 15% IPC and 6GHz. You end up at M4 level. 2.5 years later. It's not any better in SPECint.

 

[Hulk]

'heat' is a function of your process node lmao.

No, heat is a function of tranistors switching. All processes create heat from this mechanism unless you know of something new on the horizon I haven't heard of?

The heat flux is a problem in modern processors and is getting more problematic as the nodes get smaller the flux increases. If you have never had classes in thermodynamics or heat transfer I apologize for the terminology. Basically it's hard to move a lot of energy (heat) from one place to another when the area the energy must move through is small and the temperature difference between the two surfaces isn't high. This of course is why liquid nitrogen is used to record setting frequency attempts.

It would be relatively easy to run modern processors at 5.7 or even 6GHz all-cores under load if you could inexpensively keep them cool. But you can't and no process is going to fix that. The hot spot and increased flux requirements as nodes decrease only make matters worse as the area is decreasing and yet the power seems to be holding steady or even increasing.

 

[branch_suggestion]

Nope, do the 1T math. Strix is ~2950 at 5.1GHz. Assume the best case scenario for Medusa: 15% IPC and 6GHz. You end up at M4 level. 2.5 years later. It's not any better in SPECint.

That is with cluster level gimmicks.
See, when people compare ARM to x86, they neglect to compare cluster level metrics.
There are pros and cons to both approaches.

 

[poke01]

That is with cluster level gimmicks.
See, when people compare ARM to x86, they neglect to compare cluster level metrics.

can you expand on this?

 

[tcsenter]

Zen 2 ~ 5 starting to look a bit like Bulldozer polishing. I certainly hope it won't be.

 

[gdansk]

That is with cluster level gimmicks.
See, when people compare ARM to x86, they neglect to compare cluster level metrics.
There are pros and cons to both approaches.

What matters most to user experience is 1T integer performance.

In servers Zen family has advantages. But it's a market where 15% IPC in 2 years will be highly competitive.

 

[gdansk]

Zen 2 ~ 5 starting to look a bit like Bulldozer polishing. I certainly hope it won't be.

Yeah, in a parallel universe where Bulldozer polishing increased SPECint 1T by 2x and core count by 2-3x.

 

[adroc_thurston]

Nope, do the 1T math. Strix is ~2950 at 5.1GHz. Assume the best case scenario for Medusa: 15% IPC and 6GHz. You end up at M4 level. 2.5 years later. It's not any better in SPECint.

M4 is 3.6k GB6 memes and that Medusa will be what, 4k? Whatever.

But it's a market where 15% IPC in 2 years will be highly competitive.

It's a different market altogether.

 

[gdansk]

M4 is 3.6k GB6 memes and that Medusa will be what, 4k? Whatever.

I got M4 at ~3850 GB6 1T. SPECint 1T 13.6 for M4 and 13.4 for that hypothetical 6GHz Medusa.
Let me clarify what I'm saying: the M4 family will be competitive with Medusa family.

And we have to wait 2.5+ years for the privilege.

 

[adroc_thurston]

I got M4 at ~3850 GB6

Oh nyo brother that's with mememath accelerators.
No can do! It's 3600 in real world™.

SPECint 1T 13.6 for M4 and 13.4 for that hypothetical 6GHz Medusa.

Disregard specint projections since 48M L3 will bloat the Apple favorite subtest (omnetpp) for Medusa to kingdom come.

Let me clarify what I'm saying: the M4 family will be competitive with Medusa family.

Yeah sure bud

 

[MS_AT]

Oh nyo brother that's with mememath accelerators.
No can do! It's 3600 in real world™.

Well, its more likely mememath will be used in Apple ecosystem than AVX512 will be used in x64 one Intel took care of that.

 

[adroc_thurston]

its more likely mememath will be used in Apple ecosystem

Apple offloads everything humanly possible to either the ANE or the GPU. It's a benchmark pump.

than AVX512 will be used in x64 one

Pretty much everything relevant that does SIMD supports AVX512 since that is what's on server for either vendor.

 

[Joe NYC]

It's completely normal.
Zen4 was also a 15% ish fmax bump on DT, and that was a single node shrink. Not two.

Zen4 wasn't repepipelined at all? It was a completely by the numbers Zen3 derivative.

But, but, but - there is a 6 GHz ceiling and a 6.00 to 6.66 death zone.

A\MD will have to leap over this dead zone to at least 6.67 GHZ to survive.