Question Zen 6 Speculation Thread

[Kepler_L2]

Nope, do the 1T math. Strix is ~2950 at 5.1GHz. Assume the best case scenario for Medusa: 15% IPC and 6GHz. You end up at M4 level. 2.5 years later. It's not any better in SPECint.

For Medusa Point it's going from 4-core CCX with 16MB L3 to 12-core CCX with 48MB L3. The performance jump will be much higher than in desktop.

 

[poke01]

For Medusa Point it's going from 4-core CCX with 16MB L3 to 12-core CCX with 48MB L3. The performance jump will be much higher than in desktop.

Cinebench 2024 scores will look drastically different

 

[Joe NYC]

For Medusa Point it's going from 4-core CCX with 16MB L3 to 12-core CCX with 48MB L3. The performance jump will be much higher than in desktop.

2 distinct dies?

 

[adroc_thurston]

Cinebench 2024 scores will look drastically different

Boring. Uninspired. Omnetpp pumping? Sign me up.

2 distinct dies?

No, they reuse the CCD. Distinct dies are lower down the mobile stack (KRK successors).

 

[Joe NYC]

No, they reuse the CCD. Distinct dies are lower down the mobile stack (KRK successors).

Well, Kepler said from 4 core 16 MB to 12 core 48 MB L3 for Medusa Point.

So, if the low-end product is also chiplet based, it would make sense to make a cheaper 4 core dies for it, rather than wasting 66% of the die, disabling cores.

Or even better, have a 12 core CCD to support 8 and 12 core SKUs and a 6 core CCD to support 6 and 4 core SKUs. Then this 6 core CCD could work for continuation of x600 parts for low end desktop. and 4 core SKUs for low end mobile.

 

[branch_suggestion]

can you expand on this?

SME is nice for mobile workloads, cheap extra 1t perf.
But for desktop and server where many cores are maxed out, it is a waste of space.
It helps one thread out of many, how beneficial it is in the real world is questionable.
Also shared L2 clusters of 4 or so cores vs private L2/shared L3 clusters of 8-12 cores, different designs for different goals.

 

[Kepler_L2]

Well, Kepler said from 4 core 16 MB to 12 core 48 MB L3 for Medusa Point.

So, if the low-end product is also chiplet based, it would make sense to make a cheaper 4 core dies for it, rather than wasting 66% of the die, disabling cores.

Or even better, have a 12 core CCD to support 8 and 12 core SKUs and a 6 core CCD to support 6 and 4 core SKUs. Then this 6 core CCD could work for continuation of x600 parts for low end desktop. and 4 core SKUs for low end mobile.

I'm saying that Strix has a 4-core Zen5 CCX with 16MB L3, while Medusa Point will have a 12-core Zen6 CCX with 48MB L3.

 

[poke01]

SME is nice for mobile workloads, cheap extra 1t perf.

It’s only used in Geekbench so far. So far no other cross-platform applications takes advantage of SME. Those CB2024 scores you see reflect that of 526.blender. Apple has increased floating point by a huge margin for M4. AMD should beat that 170+ score with Zen6, it will be good marketing too.

different designs for different goals.

Correct, so far AMD has been designing for server first, desktop second.

and it shows. I’m hopeful for Zen6 they give more focus to laptop/mobile than desktop.

You can have more innovative designs on mobile.

 

[branch_suggestion]

It’s only used in Geekbench so far. So far no other cross-platform applications takes advantage of SME. Those CB2024 scores you see reflect that of 526.blender. Apple has increased floating point by a huge margin for M4. AMD should beat that 170+ score with Zen6, it will be good marketing too.

Worse than I thought, classic Apple.

Correct, so far AMD has been designing for server first, desktop second.

Z6 is the first with bespoke designs for client and server, now we can finally see an uncompromised Zen everywhere.

and it shows. I’m hopeful for Zen6 they give more focus to laptop/mobile than desktop.

Yes, Client is mobile first design for sure, thankfully N2 Nanoflex allows for high enough clocks to achieve desktop goals too.

You can have more innovative designs on mobile.

ATX still refuses to die, so cannot argue here.

 

[Joe NYC]

I'm saying that Strix has a 4-core Zen5 CCX with 16MB L3, while Medusa Point will have a 12-core Zen6 CCX with 48MB L3.

I see, I misunderstood. Yeah, those will be massive performance gains of Medusa Point vs. Strix Point.

I am still curious how AMD will handle low end of Zen 6. Zen 5 Kraken level and below.

 

[adroc_thurston]

I am still curious how AMD will handle low end of Zen 6

Monodies on something N3. Probably N3p. Or c.

Zen 5 Kraken level and below.

Distinct dies are lower down the mobile stack (KRK successors).

Reading isn't hard.

 

[Joe NYC]

It’s only used in Geekbench so far. So far no other cross-platform applications takes advantage of SME. Those CB2024 scores you see reflect that of 526.blender. Apple has increased floating point by a huge margin for M4. AMD should beat that 170+ score with Zen6, it will be good marketing too.

There are some workstations and server workloads that can utilize Intel AMX instructions. So, I would look there, to server / workstation benefits, because that's priority for AMD.

Correct, so far AMD has been designing for server first, desktop second.

and it shows. I’m hopeful for Zen6 they give more focus to laptop/mobile than desktop.

You can have more innovative designs on mobile.

The core will likely be the same. The best we can hope for, for client, that AMD will get enough time to optimize 1T performance, which did get enough love in Zen 5.

 

[Joe NYC]

Monodies on something N3. Probably N3p. Or c.


Reading isn't hard.

Well, distinct dies could be distinct by being monolithic vs. chiplet or chiplet with 2 distinct CCDs with different core counts.

If the packaging cost is not prohibitive, AMD might want to get out of making monolithic dies altogether.

Maybe 2 distinct CCDs dies and 3-4 distinct IODs, and then a number of permutations of these for full spectrum of SKUs.

AMD market share in client will be much higher than today, based on current trends, so there will be more units sold of each SKU.

 

[adroc_thurston]

Well, distinct dies could be distinct by being monolithic vs. chiplet or chiplet with 2 distinct CCDs with different core counts.

I'd say tile for that case.

If the packaging cost is not prohibitive, AMD might want to get out of making monolithic dies altogether

Cost no, volume yes. Monodie on FCBGA is still the easiest volume fill.

Maybe 2 distinct CCDs dies and 3-4 distinct IODs

No, no need to add packaging overhead on MSNB parts.

AMD market share in client will be much higher than today, based on current trends, so there will be more units sold of each SKU

Which is why KRK replacements are monodie!

 

[Joe NYC]

Zen2: 72mm²
Zen3: 81mm²
Zen4: 66mm²
Zen5: 66mm²
Zen6: 75mm²

According to this Tweet, the CCD in Strix Halo is indeed 66 mm2.
And according to measurements, Granite Ridge CCD is 70 mm2.

So, perhaps, AMD really made a bespoke CCD for Strix Halo.

Looking at the die, and the short side shrunk implies GMI is gone

https://twitter.com/x/status/1891364341976371566

 

[adroc_thurston]

So, perhaps, AMD really made a bespoke CCD for Strix Halo.

Not 'perhaps'. It is one.

Looking at the die, and the short side shrunk implies GMI is gone

TSV columns are gone too!

 

[Joe NYC]

Not 'perhaps'. It is one.

TSV columns are gone too!

Looks like 307.26 mm2 for SOC (IOD). That's a monster.

I wonder if AMD should break it up for Medusa Halo, to maybe a base die on N6, with analog + SRAM + memory controllers and top die on N3

 

[Glo.]

The only thing interesting to me is whether Medusa Strix and Halo and Zen 6 desktop share the same exact CPU die, and only differ by IOD.

That would be incredible from production scaling.

 

[Joe NYC]

The only thing interesting to me is whether Medusa Strix and Halo and Zen 6 desktop share the same exact CPU die, and only differ by IOD.

That would be incredible from production scaling.

And also saving design time / validation resources.

 

[yuri69]

I'm saying that Strix has a 4-core Zen5 CCX with 16MB L3, while Medusa Point will have a 12-core Zen6 CCX with 48MB L3.

This begs the question, why AMD went this way to scale Strix down to 4 cores from Phoenix's 8 and introduce heterogeneous SKU problems at the same time? Having 12 full cores - even beefier than Zen 5 - with a super-giga-TOPS-engine on a very pricey process sounds very unAMDish.

 

[leoneazzurro]

Because Strix Point is monolithic and dedicated to the mobile, and they wanted to go up to 12 cores nevertheless, for MT performance but at the same time they wanted to save as much money as possible by cutting down as much as die space as possible without affecting their performance targets.
If the rumors about Zen6 are right, Strix's successor will not be monolithic and it will share the CCD with the desktop variants. So it makes more sense to beef up the shared CCD and have probably a different IOD.

 

[LightningZ71]

A "what if" question here:
We have a solid rumor that Intel is working on an 8+16 x 2 desktop processor. We also have solid rumors that AMD's next CCD is 12 cores and probably a mix between P and C cores. It is mathematically unlikely that AMD's mixed 24 cores with SMT will match or even be close to Intel's 48 mixed cores in MT throughput.

Does AMD make a desktop part with 3 or 4 CCDs on AM5? It seems reasonable that there would be bespoke IODs for desktop, mobile and mobile Halo. Given that, it's possible for AMD to make the desktop package support 3+ CCDs.

 

[Gideon]

I'm saying that Strix has a 4-core Zen5 CCX with 16MB L3, while Medusa Point will have a 12-core Zen6 CCX with 48MB L3.

Is it certain it's 12x Zen6 not some percentage of them Zen6c?
Or are you saying that regardless, they'll all be on the same ring anyway?

 

[StefanR5R]

It is mathematically unlikely that AMD's mixed 24 cores with SMT will match or even be close to Intel's 48 mixed cores in MT throughput.

At these high core counts, when inferring performance per socket, it's time to think more in terms of Watts per socket and less in terms of cores or threads per socket.

The other aspect is that beyond such core counts, either the computer's sole purpose is to run Cinebench all day, or its purpose is to process realistic datasets and therefore this computer gets equipped with multichannel ECC RAM.

 

[reaperrr3]

It is mathematically unlikely that AMD's mixed 24 cores with SMT will match or even be close to Intel's 48 mixed cores in MT throughput.

It is mathematically unlikely that 24C Medusa Ridge will match or even be close to that 48C monster from Intel in manufacturing cost, power consumption at competitive clocks and (r)etail price, too.

And AMD will probably still win in a lot of workloads.

Is it certain it's 12x Zen6 not some percentage of them Zen6c?
Or are you saying that regardless, they'll all be on the same ring anyway?

They'd certainly all be on the same ring one way or another, but there's a serious factor speaking in favor of an all-Zen6 CCD:

The CCD's layout.

If Zen4c and Zen5c are anything to go by, the c variants are compressed along both axes.
In APUs, where the CPU cores only make up like 15-25% of the area, or c-only CCDs, you can fully leverage that.
But in a CCD with big cores, no matter where you place the c cores, you'd lose the gains along one of the axes, as the CCD dimensions will be determined by the big cores along at least one axis. In other words, mixing Zen6 and Zen6c in a CCD would result in roughly 50% of the c area gains getting lost to unused whitespace.
In that case, might as well go with full Zen6 cores only and just aim for higher MT perf so you can ask somewhat higher prices to make up for the slightly bigger CCD size.